The size of the testfile has been 4x the size of the cache on the LSI 9260, so there is a small bit of cache in the results.

The red line in the lates graph is the WB cache on the LSI, it totally changes the way iops are handeled, WT is Write Through of course.

I'll check the profiles for the missing 0, the size of the testfile used is still correct (I've checked while doing the tests).