What to Expect From AMD at ISSCC 2011

[rcofell]

Agreed, it's the best of both worlds when it comes to multithreading and IPC.

If you're a guy who doesn't need more than 4 cores, the cores get the FPU and cache to themselves and thus more single threaded performance.*

If you're a guy who likes threaded applications, you get to leverage the threaded power of the architecture for more threaded performance.

*I'm curious to know if the Bulldozer design tries to prioritize single threaded apps to their own modules, does anyone know if this is the case?

I would expect that responsibility ultimately ends up at the OS thread scheduler's mercy (or use of direct thread binding). It should still pose a similar situation as Hyper-Threading/SMT, the scheduler could use whatever logical processors it wants, however it *might* not necessarily know how to optimize for the underlying micro-architectural implications, e.g. the logical to physical mapping and their resource-sharing relation.

The more I hear about Bulldozer, the more I see it as an adaptation of the ideas inherent in the UltraSPARC T2/3 architecture, with AMD mainly emphasizing single-thread latency instead of going all out on throughput