Quote Originally Posted by terrace215 View Post
The module design ALSO involved making the non-shared elements leaner (max 2 ALU ops in parallel) than the current cores in some aspects.
First of all AMD is not disclosing all the details of the integer core organization(those AGen units could also do some math ops for example).Second of all ALU units in 10h were hindered in many ways(uops couldn't switch lanes),3rd ALU was there just for a possibly better OoO execution opportunity ,under utilization problem was present,3rd AGU was redundant as AT was told,etc. Now we have leaner and meaner integer core that can easily be 20% faster than previous 10h integer unit(this is an end effect which counts in all the new goodies AMD brought into Bulldozer design as extremely improved prefetching,branch prediction,full OoO loads/stores,double L/S BW to L1 cache,decoupled predict and fetch pipelines,branch fusion,unified integer scheduler for math and address ops,shared L2,prediction directed instruction prefetch etc).

PS Note the wording : "Throughput advantages for multi threaded workloads without significant losses on serial single-threaded workload components"
This clearly shows that they mean what I already wrote in my previous post: there is minimal loss for 2 threads(per thread) when both are being executed in parallel inside a module .