[NEW STUFF] SANDYBRIDGE LGA2xxx

[dartaz]

nice, thx for the pics.

So 2,5mb L3 per core confirmed. Also interesting to see that the L1I is now 8 way associative instead of 4 way. Higher association für L3 was kinda expected for the bigger size.

No, it has 20MB L3 shared cache which means that every core can use the whole 20MB cache

[terrace215]

No, it has 20MB L3 shared cache which means that every core can use the whole 20MB cache

I don't think he implied differently. Besides, the L3 is in fact in 2.5MB/core slices, interconnected by a ring bus.

[Hornet331]

I don't think he implied differently. Besides, the L3 is in fact in 2.5MB/core slices, interconnected by a ring bus.

Nehalem has also sliced L3 cache.

Indeed its shared, but it still is physically allocated to a core.

[terrace215]

Nehalem has also sliced L3 cache.

Indeed its shared, but it still is physically allocated to a core.

Well, the -EX does.

[Hornet331]

Well, the -EX does.

27.jpg

Not only the EX

[terrace215]

Not only the EX

Check out:

http://www.hotchips.org/archives/hc2...tel-NHM-EX.pdf

The N-EX L3 is like what comes with SB. The other Nehalem/Westmere L3s are not, "sliced" though they may also be.