Quote Originally Posted by savantu View Post
What's your point, somehow I am missing it ? What do execution units have to do with executing threads simultaneously ?

Maybe instead of amateur sources and interpretations, we should look into real technical articles, done by the people who invented this technologies and which are published at conferences and tech journals.

I've attached a diagram of the a Netburst execution core to show the simultaneous execution of 2 threads : you can find it in this paper
ftp://download.intel.com/technology/...technology.pdf
Oh, I didn't know that Intel invented SMT. Several people cite sources dating back to the early 90s, like these: http://citeseerx.ist.psu.edu/viewdoc...=rep1&type=pdf

Back to my posting: I linked to an Intel slide in an article, which didn't allow direct linking. Fixed that now.

My point is: There is some misunderstanding about when and where those two threads in a SMT core are active. I wanted to show, that during each cycle, both threads could be executed on the available execution units. In other units, like the decode or retirement units of the Netburst architecture (see the paper linked by you) , the threads are being decoded/retired in alternating cycles.

Since SMT actually is about simultaneously issueing instructions of multiple threads to a set of EUs to make better use of them, the image I posted should serve well to understand that. OTOH the sharing of some of the other resources (like decoder, cache, RF) as shown by the Netburst pipeline image is not about avoiding underutilization but causing overutilization (except one thread stalls due to a cache miss or so).