X48 Rampage Formula Preview.

[Alien Grey]

Like I said before. Trying to have it stable at 9 X 470MHz and DDR 1199MHz with tRD 6 and tREF 16120T wasn't a complete waste of time.


I know now that the BSOD 0x00000124 has something to do with the memory on the ASUS Rampage Formula board. It doesn't allow me to lower the CPU Voltage without triggering the BSOD.

It's possible to use a little bit less CPU voltage when you use the DRAM CLK Skew on Channel A/B.

This is with DRAM CLK Skew on Channel A Delay 50ps and DRAM CLK Skew on Channel B Normal. I could lower the CPU Voltage from 1.31250 to 1.30000 in the BIOS and keep it stable but I have to use CPU GTL Voltage Reference 0.65X.





To have it complete stable you should try to find a NB Voltage that let you run it with a difference of 1T between Channel A and Channel B. It's possible that you don't have to delay Channel A with 50ps and Channel B normal but keep Channel A on Normal and advance Channel B with 50ps.


My BIOS settings:

Ai Overclock Tuner [Manual]
CPU Ratio Setting [9.0]
FSB Strap to North Bridge [400MHz]
FSB Frequency [450MHz]
PCIE Frequency [100MHz]
DRAM Frequency [1199MHz]
DRAM Command Rate [2N]
DRAM CLK Skew on Channel A [Delay 50ps]
DRAM CLK Skew on Channel B [Normal]
DRAM Timing Control [Manual]
Refresh Period [16120]
DRAM Static Read Control [Disabled]
Ai Clock Twister [Lighter]
Ai Transaction Booster [Manual]
Common Performance Level [06]
Pull-In of CH A/B all disabled
CPU Voltage [1.30000V]
CPU PLL Voltage [1.50V]
North Bridge Voltage [1.29V]
DRAM Voltage [1.80V]
FSB Termination Voltage [1.20V]
South Bridge Voltage [1.05V]
SB 1.5V Voltage [1.50V]
Loadline Calibration [Disabled]
CPU GTL Voltage Reference [0.65X]
NB GTL Voltage Reference [0.67X]
DRAM Controller Voltage REF [Auto]
DRAM Channel A/B Voltage REF [Auto]
CPU Spread Spectrum [Disabled]
PCIE Spread Spectrum [Disabled]
CPU Clock Skew [Delay 200ps]
NB Clock Skew [Delay 100ps]

It was LinX stable with the NB Voltage at 1.27V in the BIOS but I have to use 1.29V to have a difference of 1T between Channel A and B as you can see in the EVEREST screenshot.





Now it's complete stable with CPU Clock Skew Delay 200ps and NB Clock Skew Delay 100ps with less voltage.





The question is how can I make it stable now at 9 X 470MHz and DDR 1253MHz with tRD 6 and tREF 16120T?