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Thread: Ex AMD designer: Bulldozer to disappoint

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  1. #1
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    Quote Originally Posted by Solus Corvus View Post
    I wouldn't compare Bulldozer and PhII cache structure based on any similarity in a block diagram. The caches in BD will be significantly worked over, if they have any similarity at all.

    Since the the first Bulldozers are rumored to not have any sort of speculative multithreading capability, the main focus seems to be in explicit multithreading (multiple threads, multiple programs, etc). Given that design focus it's doubtful that they forgot to include enough intercore bandwidth.
    well anyways the benchmarks for inter core bandwidth is showing I7 to have 33.6 gbs while phenom II has 5.27 gbs that's a huge difference.

    I'm little lost on what this "speculative multithreading" is suppose to be.

    I though bulldozer was more about parallel threading.
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    OTOH, who says Bulldozer isn't built by hand? Who says Intel's chips are non-synthesized?


    Starting with Nehalem and K10, all of the x86 chipmakers' chips are extensively modularized, which means they are bound to have synthesis comprising some parts of the chip area. Critical speedpaths are however, ensured to be handtweaked and such.


    Only Bobcat is a fully HLS design AFAIK, and that does not impact it that much when it is aimed towards usability at lowest power usage (you're not gonna touch the high clockspeeds etc.).
    Quote Originally Posted by radaja View Post
    so are they launching BD soon or a comic book?

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    Quote Originally Posted by Macadamia View Post
    OTOH, who says Bulldozer isn't built by hand? Who says Intel's chips are non-synthesized?
    .346 micron^2 for an SRAM cell on 45nm hints at hand optimized circuits.

    this whole argument is started by this guy who wants attention or something in case you havnt noticed.

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    Well, it's a fact that all recent x86 processors from Intel/AMD have portions that are both synthesized and non-synthesized, and likewise for many designs from other core-logic companies. In fact, if you look at die photos as far back as the Intel 386 you can see a good chunk of the control logic is synthesized. As time has gone on larger and larger swaths are now synthesized, since designs are much larger and complicated than they used to be, and from a business standpoint deadline/resource/budget constraints have made the shift necessary. Unfortunately, one result is design layouts aren't as elegant looking as they used to

    Performance-wise, synthesized logic for all intents and purposes has worse timing/area efficiency and potentially reliability than custom designed logic, but as mentioned the mixed designs of today make sure the critical datapaths (ALUs, SRAMs, etc.) are hand-tweaked to mitigate most of this.

    Now whether or not Bobcat will be a fully HLS design comes down to semantics and the implementation it's embedded in, as I'm sure a number of hand-tweaked components (SRAM + various datapath components) will be included as hard macros, so it would depend on how you assess them. Up until now I've just considered it a design much more abstracted to the RTL level with the physical implementation depending on the application constraints, like area/timing/power requirements and the process built on.

    Quote Originally Posted by Chumbucket843 View Post
    this whole argument is started by this guy who wants attention or something in case you havnt noticed.
    Exactly



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    Quote Originally Posted by demonkevy666 View Post
    well anyways the benchmarks for inter core bandwidth is showing I7 to have 33.6 gbs while phenom II has 5.27 gbs that's a huge difference.
    I'm saying that drawing any conclusions about BD based on PII is a bit premature.

    I'm little lost on what this "speculative multithreading" is suppose to be.
    To put it in (extremely) simple terms: speculative multithreading (SpMT) is about using multiple cores to speed up a single thread.

    I though bulldozer was more about parallel threading.
    It is, but IMO it is also laying the groundwork for SpMT in future versions of the architecture.

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    Quote Originally Posted by Solus Corvus View Post
    I'm saying that drawing any conclusions about BD based on PII is a bit premature.


    To put it in (extremely) simple terms: speculative multithreading (SpMT) is about using multiple cores to speed up a single thread.


    It is, but IMO it is also laying the groundwork for SpMT in future versions of the architecture.
    Drawing any kind of Conclusion positive or negative is in fact premature. But this guy, just like ALL OF US here has a right to his opinion even if it is Disgruntled! Some folks think it (BD) will kick @$$ and some think it will get its @$$ kicked! Either way, both sides are right until the product ships and makes one side look knowledgeable and the others side look clueless.
    Quote Originally Posted by Movieman
    With the two approaches to "how" to design a processor WE are the lucky ones as we get to choose what is important to us as individuals.
    For that we should thank BOTH (AMD and Intel) companies!


    Posted by duploxxx
    I am sure JF is relaxed and smiling these days with there intended launch schedule. SNB Xeon servers on the other hand....
    Posted by gallag
    there yo go bringing intel into a amd thread again lol, if that was someone droping a dig at amd you would be crying like a girl.
    qft!

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