Ex AMD designer: Bulldozer to disappoint

[Solus Corvus]

I think you misunderstand the timescale(s), or that two different things are involved. They're committed to shipping it (the BD microarchitecture) because that's all they have right now. It's too late to make significant changes in the arch. To start with another *microarchitecture*, you're looking at 5 years. However, if the *implementation* of the BD microarchitecture is struggling, there can very well be delays as they attempt to tune the silicon as best they can. Make sense? To me, maier's comments are not at all inconsistent with the comment by Glew.

I understand your hypothetical timescale just fine. I just think that extreme case is unlikely and so it wasn't really part of my side of the discussion.

Both Glew and Maier point to the arch being good but the first chips you see will not live up to expectations. But there are no specifics about what the problem supposedly is. It's not clear if it just needs a lot of tweaks and optimizations before being good or if it's something more serious that will take a couple of revisions and a shrink. If it just needs some tweaks in the arch and silicon before being good then it would make sense to push it back ~>=6mo and have better reviews at launch. But if it's something more serious then they may as well release on schedule since the extra time probably won't improve initial impressions much - and immediately move on to fixing issues for the next version. What you are suggesting is that not only is there a serious problem that won't be easily fixed in the first version but that there are so many small problems still that they will also miss release by a whole year. Or, as per your most recent suggestion, that the whole arch will have to be scrapped and they still can't squeeze out a sub-par chip sooner then a year late. IMO, that seems like a rather low opinion of AMD's engineering skills, but that's your prerogative.

To me also, Maier's comments and Glew's are consistent with each other. I just don't think their comments are consistent with yours. They are saying that AMD will be shipping first silicon that's below expectations. They haven't suggested, as you, faud, and others have, that it will be horribly late and/or that the architecture is unsound. While I will admit that there is some possibility of those conditions coming true, I'm not going to assign a very high probability to that outcome without some more solid evidence. I have yet to see you give even a small probability of being true to the suggestion by others that bulldozer will be ok and/or on time. Personally I admit both outcomes are possible, but that the most probable outcome lies somewhere in the middle. I have yet to see a rational reason to take the extreme perspective in this speculation.

[Solus Corvus]

Fine, don't respond. It's all peachy when you think you can refute your interlocutor with a few cleaver sentences. But once it comes to actual dialog, you are nowhere to be found.

Oh well, this will still be a useful thread to come back to in ~9-21 months for links and reading material.

[Chumbucket843]

this guy, cliff maier. has a PhD in electrical engineering with a lot of experience in chip design and he also has a law degree and practices too?! ok.

originally posted by attention wanter >
I was one of the team of 18 who designed Athlon 64 and Opteron. I designed CPUs for more than a decade for AMD, Sun, and Exponential Technology. I have a Ph.D. in electrical engineering and my dissertation involved research on a particular type of CPU.

I don't think I am "ignorant of the nature of CPUs."

so it took 18 people at AMD to design a cpu that could beat netburst? keep in mind intel has a team of 700+ engineers. this is amazing.

[Solus Corvus]

Yeah, I would trust Glew before Maier. Maier comes off as self-promoting and bitter. But after all his name dropping to artificially inflate his credibility he doesn't know a single thing about Bobcat even though that supposedly has samples already.

And I'd still like terrace215 to clarify how Maier knows what the final performance of Bulldozer will be like if it is really 18 to 21 months away. Or how Glew knew the performance 23 to 26 months in advance. IMO, even if it's only 9 months out, it'd still be too early to say how the final silicon will perform with accuracy.

[Donnie27]

http://forums.macrumors.com/showpost...&postcount=612


On paper bulldozer is a lovely chip. Bulldozer was on the drawing board (people were even working on it) even back when I was there. All I can say is that by the time you see silicon for sale, it will be a lot less impressive, both in its own terms and when compared to what Intel will be offering. I don't really want to reveal what I know about Bulldozer from my time at AMD, nor do I want to go into details of what my friends are telling me.


lots more back and forth on that thread follows and precedes that post...

But you know this guy has generated hate with folks all over the web, right?

I also gave some facts about changes in personnel and design methodology. I also pointed out that AMD has consistently underperformed Intel except for a three year period. I explained why Intel was wrong in that three year period, and why Intel had righted themselves. I gave evidence explaining that, since the end of that three-year period, the old pattern of AMD under-performing Intel has resumed. I gave evidence for why this will continue.

Even if you were right, you're talking about one narrow market segment. Every once in awhile AMD manages to beat Intel at something. For K6 it was "low end desktops sold by retailers to consumers." For K8 it was servers, supercomputers, and workstations. They've never done squat in mobile, which is the fastest growing segment. They've never done squat in handhelds. They've given up their lead in workstations/servers. They've lost their design wins in high end desktops. They're back to the same low end desktop stuff that was their only source of revenue from 1969 to 2002. They can't make make any money if they are second best and only in one or two market segments.

Been flamed saying less

Yes it would be completely stupid for Intel to grant nVidia a Free License while paying nVidia a fee! (Problem #1)Then nVidia takes this platform meant for Apple and ships them to everyone else. This would then cause Intel to loose money on platform sales in the much wider general market.

Radical? I hope AMD is in some kind of talks with Intel to solve the nVidia problem. If I'm AMD I'd think selling Chipsets (like ATI used to sell Intel chip-sets) to Apple is better than selling them nothing. No One has to worry about AMD pulling a Problem #1 like nVidia. I'd bet Intel would be willing to agree to or with AMD over nVidia any day of the week!

Stranger things have happened!

[demonkevy666]

Yeah, I would trust Glew before Maier. Maier comes off as self-promoting and bitter. But after all his name dropping to artificially inflate his credibility he doesn't know a single thing about Bobcat even though that supposedly has samples already.

And I'd still like terrace215 to clarify how Maier knows what the final performance of Bulldozer will be like if it is really 18 to 21 months away. Or how Glew knew the performance 23 to 26 months in advance. IMO, even if it's only 9 months out, it'd still be too early to say how the final silicon will perform with accuracy.

back then bulldozer wasn't made out to be clusters cores into modules .

[Dresdenboy]

back then bulldozer wasn't made out to be clusters cores into modules .

No, the MCMT design is rather old and has been known for a while to both Intel and AMD before the Bulldozer project started, according to Andy Glew. The problem, which all of us outside of AMD have, is that there is no published research, how such an architecture performs. The same for the multi level based architecture by Glew (Multi Star), which might be the basis for Bulldozer 2, which would then be capable of executing threads on more than one cluster. Intel is working on something similar (see research done by Gonzalez and others), but where I don't know, if it will hit the market some day.

For any other researched arch, there are many publications showing at least how it and it's variants perform in SPEC sub benches etc.

And BD v1 won't only be about the performance of the architecture, but also about how it reuses it's energy budget to adapt to different workloads. There is no "one size fits all" fixed architecture. It's already no more the case today (if it ever was).

[demonkevy666]

No, the MCMT design is rather old and has been known for a while to both Intel and AMD before the Bulldozer project started, according to Andy Glew. The problem, which all of us outside of AMD have, is that there is no published research, how such an architecture performs. The same for the multi level based architecture by Glew (Multi Star), which might be the basis for Bulldozer 2, which would then be capable of executing threads on more than one cluster. Intel is working on something similar (see research done by Gonzalez and others), but where I don't know, if it will hit the market some day.

For any other researched arch, there are many publications showing at least how it and it's variants perform in SPEC sub benches etc.

And BD v1 won't only be about the performance of the architecture, but also about how it reuses it's energy budget to adapt to different workloads. There is no "one size fits all" fixed architecture. It's already no more the case today (if it ever was).

http://www.brightsideofnews.com/prin...g-monster.aspx
I was thinking more along the lines of this ^
where is show BD cores in a eight core :/ no modules showen there.


what ever happened to sand tiger ?
lol dropped...

[Sparky]

I have it all figured out.

This is an ex-AMD designer because his design for Bulldozer sucked

[Donnie27]

i have it all figured out.

This is an ex-amd designer because his design for bulldozer sucked

qft, lmfao!

[demonkevy666]

here's 1 note everyone seems to skip. The two cores in a module don't have a hyper transport connection to each other, like current phenom II's and althon II's do.

[Solus Corvus]

They don't need one.

[demonkevy666]

They don't need one.

because of linked L2 cache. surely a module to module will need a bigger one.

but I wonder how a single thread will work threw that L2 cache?

will both cores get the work load or not ?

[slaveondope]

will both cores get the work load or not ?

I think this is where the surprise will be

[Solus Corvus]

because of linked L2 cache. surely a module to module will need a bigger one.

Surely? Why do you think that?

[demonkevy666]

Surely? Why do you think that?

why inter core bandwidth in phenom II isn't that great.
plus it two cores linked in module. I can't remember what review showed it though :/

anyone read any of the amd forums bulldozer says it's going to be 4kbytes(4 way) l1 cache and 265 kbytes L2 cache (16 way) 8mbs of l3 cache (64 way ?)
some how it's = to current 64 Kbytes 2 way

Dresdenboy is everywhere I read lol

[Solus Corvus]

why inter core bandwidth in phenom II isn't that great.
plus it two cores linked in module. I can't remember what review showed it though :/

I wouldn't compare Bulldozer and PhII cache structure based on any similarity in a block diagram. The caches in BD will be significantly worked over, if they have any similarity at all.

Since the the first Bulldozers are rumored to not have any sort of speculative multithreading capability, the main focus seems to be in explicit multithreading (multiple threads, multiple programs, etc). Given that design focus it's doubtful that they forgot to include enough intercore bandwidth.

[demonkevy666]

I wouldn't compare Bulldozer and PhII cache structure based on any similarity in a block diagram. The caches in BD will be significantly worked over, if they have any similarity at all.

Since the the first Bulldozers are rumored to not have any sort of speculative multithreading capability, the main focus seems to be in explicit multithreading (multiple threads, multiple programs, etc). Given that design focus it's doubtful that they forgot to include enough intercore bandwidth.

well anyways the benchmarks for inter core bandwidth is showing I7 to have 33.6 gbs while phenom II has 5.27 gbs that's a huge difference.

I'm little lost on what this "speculative multithreading" is suppose to be.

I though bulldozer was more about parallel threading.

[Macadamia]

OTOH, who says Bulldozer isn't built by hand? Who says Intel's chips are non-synthesized?


Starting with Nehalem and K10, all of the x86 chipmakers' chips are extensively modularized, which means they are bound to have synthesis comprising some parts of the chip area. Critical speedpaths are however, ensured to be handtweaked and such.


Only Bobcat is a fully HLS design AFAIK, and that does not impact it that much when it is aimed towards usability at lowest power usage (you're not gonna touch the high clockspeeds etc.).

[Chumbucket843]

OTOH, who says Bulldozer isn't built by hand? Who says Intel's chips are non-synthesized?

.346 micron^2 for an SRAM cell on 45nm hints at hand optimized circuits.

this whole argument is started by this guy who wants attention or something in case you havnt noticed.

[rcofell]

Well, it's a fact that all recent x86 processors from Intel/AMD have portions that are both synthesized and non-synthesized, and likewise for many designs from other core-logic companies. In fact, if you look at die photos as far back as the Intel 386 you can see a good chunk of the control logic is synthesized. As time has gone on larger and larger swaths are now synthesized, since designs are much larger and complicated than they used to be, and from a business standpoint deadline/resource/budget constraints have made the shift necessary. Unfortunately, one result is design layouts aren't as elegant looking as they used to

Performance-wise, synthesized logic for all intents and purposes has worse timing/area efficiency and potentially reliability than custom designed logic, but as mentioned the mixed designs of today make sure the critical datapaths (ALUs, SRAMs, etc.) are hand-tweaked to mitigate most of this.

Now whether or not Bobcat will be a fully HLS design comes down to semantics and the implementation it's embedded in, as I'm sure a number of hand-tweaked components (SRAM + various datapath components) will be included as hard macros, so it would depend on how you assess them. Up until now I've just considered it a design much more abstracted to the RTL level with the physical implementation depending on the application constraints, like area/timing/power requirements and the process built on.

this whole argument is started by this guy who wants attention or something in case you havnt noticed.

Exactly

[Solus Corvus]

well anyways the benchmarks for inter core bandwidth is showing I7 to have 33.6 gbs while phenom II has 5.27 gbs that's a huge difference.

I'm saying that drawing any conclusions about BD based on PII is a bit premature.

I'm little lost on what this "speculative multithreading" is suppose to be.

To put it in (extremely) simple terms: speculative multithreading (SpMT) is about using multiple cores to speed up a single thread.

I though bulldozer was more about parallel threading.

It is, but IMO it is also laying the groundwork for SpMT in future versions of the architecture.

[Donnie27]

I'm saying that drawing any conclusions about BD based on PII is a bit premature.


To put it in (extremely) simple terms: speculative multithreading (SpMT) is about using multiple cores to speed up a single thread.


It is, but IMO it is also laying the groundwork for SpMT in future versions of the architecture.

Drawing any kind of Conclusion positive or negative is in fact premature. But this guy, just like ALL OF US here has a right to his opinion even if it is Disgruntled! Some folks think it (BD) will kick @$$ and some think it will get its @$$ kicked! Either way, both sides are right until the product ships and makes one side look knowledgeable and the others side look clueless.

[demonkevy666]

I think those that conclusion is form the comment that it 1.8 times performance for dual thread instead of the 1.9 times scaling is with normal added cores.

[BeepBeep2]

I think those that conclusion is form the comment that it 1.8 times performance for dual thread instead of the 1.9 times scaling is with normal added cores.

And you milk out ~80% more operating efficiency?