Vertex LE vs Crucial C300

[onex]

you have raised few issues here that should be cleared out before going any further,
the SATA 2 protocol is being saturated at ~300MBps minus a little vague overhead,
at it's theoretical capability, it is able to transfer signal up to 300MBps, yet it is losing some of it's capacity do to currently a bit irrelevant factors.
what is happening inside the SATA protocol is (or should) be the same as what is happening inside the DRAM protocol,
u got a signaling rate which is limiting the device bandwidth, well so it seems.
the SATA controllers should be well capable of delivering a much higher throughput then ~300MBps,
memory controllers has showed that with speed up to many GHz (such as AMD's platforms which can sustain up to 40GHz of mem bandwidth (or i'm mistaken, i'm unsure if it is really capable of such bandwidth and how it really operate it)
yet anyhow, controllers and CPU's are much more capable then 300MBps of streaming data.
the controller optimal speed is unknown, we only know that ONFI 2.1 is capable of delivering 166-200MBps.
now one question laying, is whether each memory chip is capable of delivering up to 200MBps of bandwidth, so generally speaking, a 10 channel X-25M raided memory cell matrix, or any other onfi 2.1 device, should be capable of delivering up to 2GBps.
and well, that somehow sounds unreasonable, and it is bugging talking about these standards and specifications, with half the data...
nothing profound can be found like this.


adder -
lol,
ran into some interesting thing,
when u convert -let's say- 15KB into MB, it doesn't equal 15MB..
what we normally miss here, is the fact that 15KB equals of course 15,360,000 Bytes, yet a MB is 1024*1024 = 1,048,576, so deviding the 15.3KKB isn't going to give u the exact bandwidth,
what u do then is dividing the 15,300,000 by an ACTUAL MB, which equals 14.6MB.. .

anyway's, back to the issue:
been looking for some info on the ONFI standart and came up with some interesting finding,
u can see MLC vs SLC market share on 2006 in this pdf by Micron,
it's a very informative document...

if u'll go through this PDF, u can see that NAND flash at 16bit IOS can reach speeds of up to 40MBps,
i'm really wondering what are the cavities which sets an 10 MLC chip array ~3 years later to operate only (if it can be said) at speeds up to ~250MBps.
this isn't the protocol of course,
it triggers the question, of what did crucial did with they're C300, whether this is all about the flash chips, or more widely,
WTH is going on .