Some benchmarks of Thuban X6 1090T

[Nintendork]

Following the trend, the name Bulldozer makes sense?


Too bad the NDA will expire in at least 1 week.

[donitsi]

Nice, 4,2G with retail chip?
Good Cinebench performance too

I wonder how stable it is with these clocks

[Hans de Vries]

Keep in mind that the AMD K10.5 cores are much smaller as the the
Nehalem cores. Here a compare at 32 nm



So the Nehalem cores are 10%-15% faster in single threaded applications
and another 20%-30% through the use of Hyper Threading. They achieve
that at a cost of being 1.8 times larger.


Regards, Hans

[ajaidev]

Keep in mind that the AMD K10.5 cores are much smaller as the the
Nehalem cores. Here a compare at 32 nm



So the Nehalem cores are 10%-15% faster in single threaded applications
and another 20%-30% through the use of Hyper Threading. They achieve
that at a cost of being 1.8 times larger.


Regards, Hans

You have hit it on the head

This is my post where i was saying the same thing...

I do stand by my est. of dual llano < dual sandy bridge < quad llano < quad sandy in performance tough.

[informal]

Hans thanks for posting that analysis ,I've been saying similar thing for a while now in Deneb Vs Nehalem threads.Now we have your post backed up with nice images you compiled for all of us to see ,good job

[Opteron146]

Keep in mind that the AMD K10.5 cores are much smaller as the the
Nehalem cores. Here a compare at 32 nm

Could you identify if Sandy has 2x256kB L2 instead the prior 2x128kB ? I think it's bigger but I am not sure.

Thanks

Opteron146

[Hans de Vries]

Could you identify if Sandy has 2x256kB L2 instead the prior 2x128kB ? I think it's bigger but I am not sure.

Thanks

Opteron146

The two SRAM tiles of the L2 cache are below the "B" of Sandy Bridge.
They are longer but also less wide as in case of Westmere so the area
is about the same in both cases.

Thanks for that picture. I published it on my blog with some thoughts added. Besides the likely double pumped FPU there might also be signs of a trace cache (directly below the execution units). Maybe you have an even higher res SB die shot to check this.

A good candidate for a Trace cache would be the larger square tile
below the L2 cache and above the location of the L1 instruction cache
in Westmere, which is located at the bottom edge in the middle.


Regards, Hans

A bit larger version:

[Dresdenboy]

So the Nehalem cores are 10%-15% faster in single threaded applications
and another 20%-30% through the use of Hyper Threading. They achieve
that at a cost of being 1.8 times larger.

Thanks for that picture. I published it on my blog with some thoughts added. Besides the likely double pumped FPU there might also be signs of a trace cache (directly below the execution units). Maybe you have an even higher res SB die shot to check this.