First Bulldozer Benchmarks

[Xoulz]

lulz...

[Napster69]

GTX 580.....HD 5999..... n now bulldozer's benchmarks??!!?! painful to swallow all in 1 day......best april fool ever...lol...:-)

[ajaidev]

Where is sandy bridge they should have used their imagination

[zir_blazer]

The first part of the question, why us. That was answered by John Fruehe of AMD's server marketing division "AMDZone has had as long track record of helping AMD owners with general questions and in getting the truth out about their [AMD] products, as well as being the seconds largest AMD self help forums second only to the AMD forums itself. We find it only fitting that we should announce the upcoming Bulldozer and Bobcat cores on AMDZone."

When asked why now? John Fruehe answers again that Simply put the Bulldozer is so far ahead of the performance curve that we feel confident that even Intel with its next generation chip will not be able to match the likeness of the bulldozer design.”

Does JF-AMD have anything to say in self defense?

[haylui]

zambezi 3.2 vs zambezi BE 3.2 has different result?

[haylui]

I would like to thank Dresdenboy for is in depth analysis of the core changes, Abinstein and AussieFX for their review of the article, Chirs Tom for testing and the use of his site, to myself for pulling an all a few all niters to get the site ready and to get this article done on time, to John Fruehe for setting us up with the system and to anyone else I forgot.

so many people doing the review???

[w0mbat]

i told DDB before that every1 will think its a joke but they wanted to release the infos right on... they said JF-AMD will back them and there wont be any doubts.

[haylui]

Finaly if all else fails AMD's Bulldozer has an aggressive cache system.

L0 cache: 4 kB (8-way associative) trace cache for each thread (or core)
L1 cache: 16 kB (4-way) data cache per core 1 cycle latency and 128 kB (4-way) instruction cache per module
L2 cache: 2 MB (8-way) per module (shared between two cores), full-speed
L3 cache: 8 MB shared between all cores, the L3 cache with a latency of 24 cycles will be able to serve up to 2 requests per (NB) clock cycle simultaneously and transfer data with 16B/clock to each of the reciepients.
L4 cache: AMD has also announced that all Black Editions and Opterons models will come with 32/64MB L4 cache made possible through chip stacking.But now a bit more about the details. The instruction fetch unit (IFU) fetches code from the L1 instruction cache (at 32 Bytes/cycle).

5 level cache system? I thought DRAM would be integrated into the core as well? lolz

[haylui]

i told DDB before that every1 will think its a joke but they wanted to release the infos right on... they said JF-AMD will back them and there wont be any doubts.

you sure the release is real?

[hurleybird]

i told DDB before that every1 will think its a joke but they wanted to release the infos right on... they said JF-AMD will back them and there wont be any doubts.

I'll beleive it when JF-AMD backs the results on April 2nd, and even then I would want an explanation about those 3Dmark GPU scores. Still, here's hoping

[Macadamia]

rofl forl

[saaya]

lol

[zir_blazer]

I'll beleive it when JF-AMD backs the results on April 2nd, and even then I would want an explanation about those 3Dmark GPU scores. Still, here's hoping

The truth is that considering that Opterons always receives first the Cores featuring major architectural improvement, means that there are pretty high chances that JF-AMD, being a high ranking AMD employee from the Server (Opteron), will be one of the first in using a Bulldozer Engineering Sample if he is not using one right now. Obviously, for everything that NDA stands for, I don't even think that we will come close to post on this Thread.
Opterons were first with K8, were first with Dual Core, were first with K10/Quad Core, were first with Six Core, and will obviously be the first with Bulldozer. Mark my words.

[haylui]

The truth is that considering that Opterons always receives first the Cores featuring major architectural improvement, means that there are pretty high chances that JF-AMD, being a high ranking AMD employee from the Server (Opteron), will be one of the first in using a Bulldozer Engineering Sample if he is not using one right now. Obviously, for everything that NDA stands for, I don't even think that we will come close to post on this Thread.
Opterons were first with K8, were first with Dual Core, were first with K10/Quad Core, were first with Six Core, and will obviously be the first with Bulldozer. Mark my words.

first with 12 cores Magny-Cours

[JF-AMD]

This is not true.

Admin, please kill this thread IMMEDIATELY.

[haylui]

This is not true.

Admin, please kill this thread IMMEDIATELY.

just take it as a joke???

[hurleybird]

Awwwww.

Still an epic April Fools.

[Florinmocanu]

some intel fans probably cried and wept for a couple of hours before realising it's an elaborate prank

[saaya]

This is not true.

Admin, please kill this thread IMMEDIATELY.

but he said he got the review system from you? why would you want it pulled now? unless... its not fake!!!!

[haylui]

but he said he got the review system from you? why would you want it pulled now? unless... its not fake!!!!

oh noes...you make the matter even more complicated

[annihilat0r]

mind=blown

[wuttz]

mind=blown

x2

[ajaidev]

looks like fruehe is super pissed...

JF-AMD:

This is TOTALLY uncool.

I could lose my job over this prank.

TAKE THIS THING DOWN NOW, DO NOT SPREAD IT.

I don't know who had this idea, but this is not good.

http://www.amdzone.com/phpbb3/viewto...?f=52&t=137560

[qcmadness]

http://www.amdzone.com/joomla/index....2&limitstart=2

A page of BS...

One thing that has been confirmed is that the Bulldozer core has been shown to be incredibly resilient during early manufacturing samples, so much so that AMD has told us that it is experimenting using the 28nm bulk silicon process with only small changes to the die. Although AMD has not confirmed that they will use half stepping, they didn’t deny it either.

32 nm SOI with Immersion Lithography
28 nm SOI with Immersion Lithography half node process

One of the first things that AMD confirmed for us was that the upcoming AM3+ will be the last of the pin grid array (PGA) and that all upcoming processor would be land grid array (LGA) more on that later.

The current AM3 Phenom II only use 938 pins, the upcoming Bulldozer and Bobcat cores will use all 941 pins. One of the benifiets of the AM3+ is that all AMD chips will be able to use DDR3 1866 (PC3 -15000) for staggering 60000MB/s as well as having advanced powersavings.

Going forward AMD’s will implement AMD’s Future socket or AMD’s Fusion socket, (Socket AF1) a massive Socket 1591 pins sock that will be the first of AMD’s next generation sock supporting DisplayPort 1.2, Full PCI Express 3.0 32 lane, and the addition of two more DDR channels allowing for quad channel memory.

[Sn0wm@n]

amdzone is an official amd site right??? if so this cant be an april fool's joke


btw welcome back amd aka the pentium killers