AMD talks up its first Fusion chip

[Motiv]

Here's a slight oddity of a question for you.

If I have a dual socket board for llano, will I get to use them in Crossfire?

[zalbard]

Here's a slight oddity of a question for you.

If I have a dual socket board for llano, will I get to use them in Crossfire?

Yeah, if you can hook up the crossfire bridge to the CPU!

[doompc]

Motiv, Llano won't have Hyper Transport for CPU Interconnect. Only integrated memory controller and PCI Express like Clarkdale/Lynnfield.

[Motiv]

Motiv, Llano won't have Hyper Transport for CPU Interconnect. Only integrated memory controller and PCI Express like Clarkdale/Lynnfield.

Shame that. Would of been interesting to see the marketing spin on a plug in upgrade that doubled CPU and GPU performance (and of course crossfire over HT).

I suppose with llano being a more mainstream CPU, it's not really needed.

[doompc]

It might support Hybrid Crossfire with the equivalent discrete GPU though. But that's more like a marketing gimmick than useful feature (1 slow GPU sucks, 2 slow GPUs still suck).

[JumpingJack]

Does 6T mean six transistors per cache cell? So Llano's cache might need more space for the same amount, but on the other hand need less energy?

P.S. Dann bist du wohl auch der Opteron der im Luxx sein "Unwesen" treibt, was? :P

Yes, 6T stands for 6 transistor, most of the cache in the last several years were based on a 6 transistor bit cell (for storing one bit), Intel implemented an 8T transistor cell in their 45 nm Nehalem, and it appears (interestingly enough) that AMD will do the same.

Logically, 8T should take up more area, depending on the layout how much more area is not going to be exactly clear unless AMD publishes a cell layout picture.

It is counter intuitive that 8T should consume less power than 6T, and all things being equal it 8T would consume more power than 6T. However, 8T allows voltage to be dropped (not as sensitive to lower voltage limit) in lower power standby, which has a net win on power.

[ajaidev]

Did you all notice the teraFLOP written there, if this is indeed written for the APU it means that they went from a gigaFLOP est. to a teraFLOP est.

[zalbard]

Did you all notice the teraFLOP written there, if this is indeed written for the APU it means that they went from a gigaFLOP est. to a teraFLOP est.

http://www.pcgameshardware.de/screen...yst-Day-03.png

Deeplinking is not allowed.



And yeah, a teraFLOPS should be pretty accurate number for the integrated GPU.

[ajaidev]

Deeplinking is not allowed.



And yeah, a teraFLOPS should be pretty accurate number for the integrated GPU.

Fixed

The last time Anand referred to this he called it a gigaFLOP class APU, if the teraFLOP moniker is truly for the APU "At stock" its wonderful news.

[Lightman]

Fixed

The last time Anand referred to this he called it a gigaFLOP class APU, if the teraFLOP moniker is truly for the APU "At stock" its wonderful news.

I've read that for TeraFLOP class architecture moniker you need 501GFLOPS performance. Still quite a bit more than HD2900 or HD3870 or HD4670 in your CPU

[Opteron146]

Did you all notice the teraFLOP written there, if this is indeed written for the APU it means that they went from a gigaFLOP est. to a teraFLOP est.

In my opinion, they are just referring to their visual computing breakthroughs by breaking the 1 TFLOP barrier.

They clearly wrote 1TFLOP GPU, not 1 TFLOP APU ;-)

Furthermore, think about the memory limitations ... ~800 Shader cores and then dual channel DDR3, which is shared with the CPU cores.

That would be not feasible in my opinion.

[vietthanhpro]

Hi Vietthanpro,
I probably should have said 6.4 Gb/s (=HT3.1) anything above that
is speculation. I could believe higher speeds on a MCM (multi chip module)
There is a lot going on in the industry to get to higher serial
communication speeds. For instance some recent news:
Engineers explore life beyond 10 Gbit links
Designers rally around 25G, but next step still a mystery
http://www.eetimes.com/news/design/s...2700195&pgno=1
Regards, Hans

Hi Hans de Vries, first is HTlink then PCIe. Why ?

[Opteron146]

Hi Hans de Vries, first is HTlink then PCIe. Why ?

Because of my post #32. Don't aks, read first ;-)

[BrowncoatGR]

In my opinion, they are just referring to their visual computing breakthroughs by breaking the 1 TFLOP barrier.

They clearly wrote 1TFLOP GPU, not 1 TFLOP APU ;-)

Furthermore, think about the memory limitations ... ~800 Shader cores and then dual channel DDR3, which is shared with the CPU cores.

That would be not feasible in my opinion.

How the GPU access memory is still an unknown really. But the GPU is made on a 32nm SOI process, so higher clockspeeds than in earlier designs might be achievable.

[Dresdenboy]

How the GPU access memory is still an unknown really. But the GPU is made on a 32nm SOI process, so higher clockspeeds than in earlier designs might be achievable.

According to Sam Naffziger, the GPU accesses memory through the XBar like the CPU cores. Shared memory model, same type of access. Maybe they added some prefetching logic, which works better for GPU typical access patterns.

[Badfastbusa]

Looks promising, but intel has my heart now.

[MrMojoZ]

Looks promising, but intel has my heart now.

Yes Intel's graphic enabled CPUs have captured the adoration of the masses. Or:
Why would you bother posting this?

I'll let you pick.

[demonkevy666]

It might support Hybrid Crossfire with the equivalent discrete GPU though. But that's more like a marketing gimmick than useful feature (1 slow GPU sucks, 2 slow GPUs still suck).

I got crossfire 3470's that don't suck they Oc to 900mhz core.... 850mhz ram, passivly.

[Nedjo]

Extensive interview with Samuel Naffziger - AMD's Senior Fellow about company's upcoming APU "Llano" - http://www.insidehw.com/Editorials/I...sing-Unit.html

[Zibi]

An even higher res Llano shot can be found at
This might be interesting for core comparisons, for example to find out, what this is (APM? more TLBs? or related to dynamic cache resizing?):

.

I see more changes:

Longer Shedulers or ALU/AGUs ??
Increased reorder buffer ??
New unit next to the FPU register?? (currently it is empty space)

[iddqd]

Worthless for enthusiasts until they improve how multi-GPU solutions work. Right now, GPUs don't play together nearly as nicely as CPUs... the implementation is incredibly clumsy and wasteful.

Great for laptops, though. Ensures that you'll at least get a half-decent integrated graphics chip.

[Manicdan]

Worthless for enthusiasts until they improve how multi-GPU solutions work. Right now, GPUs don't play together nearly as nicely as CPUs... the implementation is incredibly clumsy and wasteful.

Great for laptops, though. Ensures that you'll at least get a half-decent integrated graphics chip.

id use it for physics, probably more than enough power to do a better job than quad 3-4ghx cpu dedicated to it.

[Opteron146]

I see more changes:

Longer Shedulers or ALU/AGUs ??
Increased reorder buffer ??

Yes, this is mentioned in the articles linked previously:
http://www.xtremesystems.org/forums/...2&postcount=50

New unit next to the FPU register?? (currently it is empty space)

I think that's new ;-)
I assume that it has something to do with SSSE3/SSSE4.1. When AMD doubled the FPU from 64->128bit they basically copied the whole 64bit FPU. However there was some empty space in the end which was used for old 3DNOW! stuff and need not to be doubled. Thus it would be logical, if AMD uses that free space in the doubled FPU part with another instruction set extension.

Welcome to XS

Opteron146

[Opteron146]

Worthless for enthusiasts until they improve how multi-GPU solutions work. Right now, GPUs don't play together nearly as nicely as CPUs... the implementation is incredibly clumsy and wasteful.

Great for laptops, though. Ensures that you'll at least get a half-decent integrated graphics chip.

Apple OS will take care of this
Google for Frand Central Dispatch and CLANG/LLVM.

And then think about the current AMD - Apple rumors ;-)

[Dresdenboy]

I see more changes:

Longer Shedulers or ALU/AGUs ??
Increased reorder buffer ??
New unit next to the FPU register?? (currently it is empty space)

Additional to what Opteron146 pointed out, there was another update over 2 months ago:
http://citavia.blog.de/2010/02/09/so...o-die-7974978/

There is also something new in the L/S unit plus new D$ tags.
The ALU/AGU block became longer at the int multiplier end, maybe related to a lower power multiplier implementation or the already mentioned hardware divider support.