AMD to disclose their 32nm tech...

[Nedjo]

...and enhancements made to AMD’s x86 core that will appear in the first Fusion APU (Llano)!

One of the most important events is few weeks away - ISSCC, and it'll bring some exciting disclosures:


5.6 An x86-64 Core Implemented in 32nm SOI CMOS
4:15 PM
R. Jotwani1, S. Sundaram1, S. Kosonocky2, A. Schaefer1, V. Andrade1, G. Constant1, A. Novak1,
S. Naffziger2

AMD, Austin, TX 2AMD, Fort Collins, CO

The 32nm implementation of an AMD x86-64 core occupying 9.69mm2 and containing more than 35
million transistors (excluding L2 cache), operates at frequencies >3GHz. The core incorporates
numerous design and power improvements to enable an operating range of 2.5 to 25W and a zero-power
gated state that make the core well-suited to a broad range of mobile and desktop products.

http://www.isscc.org/isscc/2010/ISSC...nceProgram.pdf

there's also more exciting things:


5.4 The Implementation of POWER7TM: A Highly Parallel and Scalable Multi-Core High-End
Server Processor
3:15 PM
D. Wendel1, R. Kalla2, R. Cargoni2, J. Clables2, J. Friedrich2, J. Kahle2, B. Sinharoy3, W. Starke2,
S. Taylor2, S. Weitzel2, S. G. Chu2, S. Islam2, V. Zyuban4

IBM, Boeblingen, Germany 2IBM, Austin, TX
IBM, Poughkeepsie, NY 4IBM T.J. Watson, Yorktown Heights, NY

POWER7TM the next generation processor of the POWERTM family is introduced. The 8-core chip,
supporting 32 threads, is implemented in 45nm 11M CMOS SOI. The 32kB L1 caches feature 1
read port banked write for the I-cache and 2 read ports banked write for the D-cache. The on-chip
cache hierarchy consists of a 256kB fast, private SRAM L2 and a 32MB shared L3, implemented
in embedded DRAM

+


5.2 A 40nm 16-Core 128-Thread CMT SPARC SoC Processor
2:00 PM
J. Shin, K. Tam, D. Huang, B. Petrick, H. Pham, C. Hwang, H. Li, A. Smith, T. Johnson,
F. Schumacher, D. Greenhill, A. Leon, A. Strong

Sun Microsystems, Santa Clara, CA

A 16-core SPARC SoC processor enables up to 512 threads in a 4-way glueless system to
maximize throughput. The 6MB L2 cache of 461GB/s and the 308-pin SerDes I/O of 2.4Tb/s
support the required bandwidth. Six clock and four voltage domains, as well as power
management and circuit techniques, optimize performance, power, variability and yield trade-offs
across the 377mm2 die.

And no I'll not skip Intel


5.7 A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS
4:45 PM
J. Howard1, S. Dighe1, Y. Hoskote1, S. Vangal1, D. Finan1, G. Ruhl1, D. Jenkins1, H. Wilson1, N. Borkar1,
G. Schrom1, F. Pailet1, S. Jain2, T. Jacob2, S. Yada2, S. Marella2, P. Salihundam2, V. Erraguntla2,
M. Konow3, M. Riepen3, G. Droege3, J. Lindemann3, M. Gries3, T. Apel3, K. Henriss3, T. Lund-Larsen3,
S. Steibl3, S. Borkar1, V. De1, R. Van Der Wijngaart4, T. Mattson5

Intel, Hillsboro, OR 2Intel, Bangalore, India 3Intel, Braunschweig, Germany
Intel, Santa Clara, CA 5Intel, DuPont, WA

A 567mm2 processor on 45nm CMOS integrates 48 IA-32 cores and 4 DDR3 channels in a 6×4 2D-mesh
network. Cores communicate through message passing using 384KB of on-die shared memory. Finegrain
power management takes advantage of 8 voltage and 28 frequency islands to allow independent
DVFS of cores and mesh. As performance scales, the processor dissipates between 25W and 125W.

IMHO this is more exciting than Fermi deep dive! But that's just me!


One thought for contemplating: Llano's CPU part w/0 cache will be 38.76 mm^2 in QC configuration! If we'd be generous and say that L2 is of the same size, that would put CPU part of the die under 80 mm^2!! (more than twice smaller than Propus!)

Also consider that Redwood's 40nm die size is 104 mm^, and feel free to speculate about Llano size!
P.S
just for bragging right none of mainstream news site that we link here didn't write about this yet!

This time around XS is source of info!

[zalbard]

No offense, but how about using a smaller font? lol.
And comments on topic once I finish reading.

[rogueagent6]

No need for that font size.

[ajaidev]

The font size is okk it makes me feel excited hahaah

Intel shows lrb ahh i mean the cloud core yaaa but at 45nm

AMD's Llano wood be a hoot but i dont know why are they showing of Llano in such a event bulldozer would be a better choice

IBM's Power7 how interesting a design totally differnt from Power6, i do admire the PPC's a lot and i did admire apple when they used PPC now they are just like Acer/HP they dont have anything special anymore except job's face

[STaRGaZeR]

What the frack. Reported.

[XSAlliN]

Guess this guy has a 108 inch LCD as main display.

[zalbard]

The 32nm implementation of an AMD x86-64 core occupying 9.69mm2 and containing more than 35 million transistors (excluding L2 cache), operates at frequencies >3GHz. The core incorporates numerous design and power improvements to enable an operating range of 2.5 to 25W and a zero-power gated state that make the core well-suited to a broad range of mobile and desktop products.

3GHz for a starting frequency isn't bad at all.
1x core = 25W, means 4x cores = 100W, and this is without cache? about the same as most today's CPUs it seems, a bit disappointing since it's 32nm, but I hope the performance will be good enough to compensate for that.

One thought for contemplating: Llano's CPU part w/0 cache will be 38.76 mm^2 in QC configuration! If we'd be generous and say that L2 is of the same size, that would put CPU part of the die under 80 mm^2!! (more than twice smaller than Propus!)

Yeah, but don't forget L3, memory controller, etc... Edit: nevermind.

[saaya]

No offense, but how about using a smaller font? lol.
And comments on topic once I finish reading.

maybe hes using the new vaio Z?

amds atom... FINALLYYY!!!!
2.5W is still a lot though, and if it needs conventional NBs and SBs... thats not very good...

nothing about "K11"?

[zalbard]

maybe hes using the new vaio Z?

Rofl, seriously, brilliant!

[ajaidev]

3GHz for a starting frequency isn't bad at all.
1x core = 25W, means 4x cores = 100W, and this is without cache? about the same as most today's CPUs it seems, a bit disappointing since it's 32nm, but I hope the performance will be good enough to compensate for that.

Yeah, but don't forget L3, memory controller, etc...

I was under the impression that Llano does not have L3, just a 1MB L2 and a 480 SP "Evergreen based"

[zalbard]

I was under the impression that Llano does not have L3, just a 1MB L2 and a 480 SP "Evergreen based"

Ah, yeah, my bad. I mixed up different code names.

[Nedjo]

maybe hes using the new vaio Z?

amds atom... FINALLYYY!!!!
2.5W is still a lot though, and if it needs conventional NBs and SBs... thats not very good...

nothing about "K11"?

sorry about the font! I was messing around with formating, and battery on my notebook collapsed before I could have made correction! Sorry!

Anyhow, back to the topic!

here's nice assumptions about core sizes in curent 45nm CPUs, made by Hans De Vries:

[zalbard]

Why is the core without L2 so much smaller?

[ajaidev]

Why is the core without L2 so much smaller?

Because the L2 tech used by Intel is so so much better and compact as a result than the L2 tech used by AMD the result is the AMD processors fatten up due to L2's and L3's taking up a huge amount of space...

[zalbard]

Because the L2 tech used by Intel is so so much better and compact as a result than the L2 tech used by AMD the result is the AMD processors fatten up due to L2's and L3's taking up a huge amount of space...

I think you got me wrong.
Nehalem: single core size of 24.4mm^2 (excl. L2)
Shanghai: single core size of 15.3mm^2 (excl. L2)
Or maybe it's me who got you wrong?
It should really affect the performance big time, shouldn't it?

[Nedjo]

Because the L2 tech used by Intel is so so much better and compact as a result than the L2 tech used by AMD the result is the AMD processors fatten up due to L2's and L3's taking up a huge amount of space...

actually if you take look at the big picture up, you'll notice that L2 density is almost same... Intel's L3 is denser 'cos it uses different cache tiles. AMD uses same cache tiles for L3 as for L2.

[saaya]

sorry about the font! I was messing around with formating, and battery on my notebook collapsed before I could have made correction! Sorry!

no need to apologize man, yout thread, use whatever font you want
cheers for making it smaller though, its easier to read

[informal]

I think you got me wrong.
Nehalem: single core size of 24.4mm^2 (excl. L2)
Shanghai: single core size of 15.3mm^2 (excl. L2)
Or maybe it's me who got you wrong?
It should really affect the performance big time, shouldn't it?

It should make a big difference but it doesn't overall.Intel invested heavily in logic die area while AMD made smaller "core" and crammed more of it into design,while having worse cache density though. SMT does help and it gives a solid 10-30% in some workloads so it pays up in Nehalem's case(it hurts perf. in many others so often companies turn it off...).
In Penryn's case it's much worse since in server world Yorkfields get beaten by Shanghais and by a decent margin in many workloads,while the single "core" size is still much larger than the one in Shanghai(20.5mm2 IIRC Vs. 15.3mm2 for Shanghai;inferior I/O really kills Yorkfield in server arena).

On the Llano topic,I'm really looking forward to seeing this gem in action. The CPU part should be a decent improvement over K10 in power management and overall speed(due to higher core speed and possible cache optimizations),while the GPU part will absolutely crush anything from competition.

[ajaidev]

I think you got me wrong.
Nehalem: single core size of 24.4mm^2 (excl. L2)
Shanghai: single core size of 15.3mm^2 (excl. L2)
Or maybe it's me who got you wrong?
It should really affect the performance big time, shouldn't it?

actually if you take look at the big picture up, you'll notice that L2 density is almost same... Intel's L3 is denser 'cos it uses different cache tiles. AMD uses same cache tiles for L3 as for L2.

Thats true Nedjo AMD is using L2 design for the L3 cells but Intel is using denser L3 cells for Nehalem. That means if the size of the L2 is the same between the two the size of both will be same. EG 24.4mm^2 + 10mm^2 for nehalem with L2 512kb and 15.3mm^2 + 10mm^2 for a deneb with L2 512kb but the nehalem uses 256kb L2 and deneb uses 512kb L2. If AMD used a more compact sized L3 the deneb would have been far smaller.

Core size of AMD cpu's are always relatively smaller as compared to Intel. But in operation that does not make a difference just the size of the cpu die...

[Helmore]

I don't think anybody would deny the fact that Intel's current cores are quite a bit more complex than AMD's cores. Then I mainly mean Intel's front and back-end. AMD still does an admirable job though, especially considering their size.

One question, in what does a Llano core differ from a current Deneb core? Just wondering, as that Llano core seems to be a bit more complex than a current Deneb core, or the extra size is a result of power optimizations.

[mAJORD]

Some measurements for 32nm Westmere for an official 81 mm2 die size.


Core Size (Exl L2): 17 mm2

Cache density:

L2: 4.4 mm2 / MB
L3: 3.8 mm2 /MB


Everything shrunk pretty significantly, but interesting the core is still larger than 45nm K10 due to complexity.

[rozzyroz]

how will the integrated gpu compare in respects to the 5XXX series cards? I assume that it is dx11 and full featured?

[vietthanhpro]

[SIZE="2AMD, Austin, TX 2AMD, Fort Collins, CO
[/U]
The 32nm implementation of an AMD x86-64 core occupying 9.69mm2 and containing more than 35
million transistors (excluding L2 cache), operates at frequencies >3GHz. The core incorporates
numerous design and power improvements to enable an operating range of 2.5 to 25W and a zero-power
gated state that make the core well-suited to a broad range of mobile and desktop products.[/i]

A K10.5 core contain less more 25 million transistors (excluding L2 cache). It 's not a Llano CPU.

[mAJORD]

K10.5 core should have around 33Million transistors..

[G.Foyle]

Some measurements for 32nm Westmere for an official 81 mm2 die size.

81 mm² is with test circuitry included. Real die size (on substrate) is around 77 mm².