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Thread: 2009 AMD analysts day [official thread]

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  1. #1
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    The contender for the most ridiculous article of the year(or even the decade ):
    Fuad Abazovic's latest and "greatest":
    http://www.fudzilla.com/content/view/16425/1/
    Bulldozer has two quad cores stitched <---[what the hell... ]

    Written by Fuad Abazovic
    Friday, 13 November 2009 11:01

    Image

    Some parts shared

    According to Chuck Moore, Corporate Fellow and CTO Technology Development of AMD, the new Bulldozer X86 architecture has “two tightly linked cores.” [After this it all goes downhill and he gets lost in the dark woods of stupidity ]


    Image

    If you look at the picture above, posted in Chuck's presentation, Bulldozer has two quad cores with an integer scheduler and the two cores share two FPU 128bit FMAC schedulers. <--[]

    Each int scheduler quad <--[Oh my God ] has its own L1 cache that talks with L2 shared cache used by both cores and FPU units and finally, the last layer has Shared L3 cache as well as Nortbridge support. (You lost me at 'each'. sub.ed.)

    This CPU will be designed to easily interconnect with graphics, but such a product probably won't launch before 2012. AMD claims Bulldozer and Bobcat are two new x86 cores targeting different usage models.

    "Bulldozer will be a completely new, high performance architecture for the mainstream server, desktop and notebook PC markets that employs a new approach to multithreaded compute performance for achieving advanced efficiency and throughput. Bulldozer is designed to give AMD an exceptional CPU option for linking with GPUs in highly scalable, single-chip Accelerated Processing Unit (APU) configurations. Bobcat will target the low power, ultrathin PC markets with an extremely small, highly flexible, core that also is designed to be easily scaled up and combined with other IP in APU configurations,” claims AMD.

    AMD didn’t save its breath to attack Intel for stitching two cores together, and in two years from now, it plans to stitch two cores that will share some parts. As far as we know 8-core Nehalem EX can get to 8 native cores even at 45nm and we are quite sure that for late 2010 Intel plans to launch an 8-core 32nm Westmere based CPUs. <--- [totally clueless and lost ]

    AMD plans Bulldozer for desktop and server market in 2011.
    He has outdone himself with this "piece of news". Newsflash Fudo,you have no idea what you are talking about!
    There is a Bobcat related article too,not much less ridiculous than this one of course.Enjoy!

  2. #2
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    The choice for APU's (LIano, Ontario) was SOI GPU or bulk CPU. According to Fuad, AMD has chosen the second possibility. Both should be made in 40 nm bulk with some RV8x0 GPU. Interesting for me.

  3. #3
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    Quote Originally Posted by Behemot View Post
    The choice for APU's (LIano, Ontario) was SOI GPU or bulk CPU. According to Fuad, AMD has chosen the second possibility. Both should be made in 40 nm bulk with some RV8x0 GPU. Interesting for me.
    Huh? Unless I'm mistaken, I seem to remember Bergman alluding to the fact they're SOI with the comment that the GPU portion is not a risk item on SOI.

    While AMD's future Fusion offering would certainly have cost/size advantages when used in a game console... it's still a year out and I think the next xbox360 revision should prove to be interesting at a sooner date. Also, like chumbucket mentioned, just because it has a decent amount of SPs doesn't mean the performance is the same as it would be for a discrete implementation... there are still issues of TDP and more importantly the memory interface (I really wish they would've leaked some details on the Fusion memory controller ).

    Now what I'm waiting for is the point when the GPU portion will be more native and not necessarily require going through a software driver, which AMD seems to acknowledge.



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    Quote Originally Posted by rcofell View Post
    Now what I'm waiting for is the point when the GPU portion will be more native and not necessarily require going through a software driver, which AMD seems to acknowledge.
    I am interested in this as well. It seems to be a possible conclusion to this GPU + CPU combining trend.

    But it would require a new instruction set to be able to access those GPU functions, hopefully standardized. Otherwise the only way to access the gpu will continue to be through drivers + API.

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    Quote Originally Posted by rcofell View Post
    Huh? Unless I'm mistaken, I seem to remember Bergman alluding to the fact they're SOI with the comment that the GPU portion is not a risk item on SOI.
    Well, I know, Fuad; but there are some other indicators, like at http://www.anandtech.com/cpuchipsets...spx?i=3673&p=4 last the picture - Brazos is not colored like 65/45/32 nm (and 28 nm is too far away from 2011). Also http://xtreview.com/addcomment-id-64...rocessors.html talks about some possibilities to TSMC test Fusion on 40 nm bulk process.

  6. #6
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    Quote Originally Posted by informal View Post
    He has outdone himself with this "piece of news". Newsflash Fudo,you have no idea what you are talking about!
    Thats not news... its already in the history books.

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