Quote Originally Posted by informal View Post
@ Face

That picture of Llano die is actually not complete ,look up a few posts.
The not-cropped picture shows much greater section dedicated to GPU,approx. ~480SP.Total die size est. 200+mm2,est. IMC is 192b wide supporting 1600Mz DDR3 memory.
Thankx for the picture :^)

It was clear that it was cropped from the DRAM IO paths, so I had
already extended that. Also the other (left) side shows a truncated
HT IO module (It seems there are four half HT units)

I had expected a 64 bit GDDR5 "side buffer" below the GPU. I wouldn't
know where they would otherwise get the memory bandwidth from...

The IMC width is 128 bit . It's exactly like the regor one. Maybe it
runs faster but it seems more logical to have a side bus with a minimum
of two GDDR5 chips with could fit in the package itself providing much
more bandwidth as the standard IMC.

The foils say it has an high frequency memory interface in a such a
way that it strongly suggest that it's GDDR5 compatible.


Regards, Hans