E-Crush,

as for making signals harmonious as you say (snychronizing) this is basically a GOOD idea. For example compensating longer signal runtimes to different RAM banks...

However I think in THIS case it is about avoiding signal interference by shifting them slightly.

A huge problem is for the 20x multiplier of our beloved 920s that so many signals derived from BClock are in exact sync. So rising and falling signals broadcast an electromagnetic pulse into neighboring traces on the board that run signals in sync. Flank meets flank and spike amplifies spike.

No, I gues sthe clock signal delays/skews are here to AVOID perfect synchronisation and thus spike adding/amplifying....


This whole thing is even more important on our previous S775 systems with it's rather analog AGTL+ bus