DFI LANparty DK P45-T2RS/T3RS (Intel P45) - News|Info|Results

[Don_Dan]

That sounds pretty good!
Just tell me how you adjusted the CPU VTT by using the 1.45v on nb.
Did you set FSB Vref on auto, were your DRAM Timing Page on "fast, fast" and did you set "Model 3, Model 3 , Model1 ?

I'm on my UD3P, don't know what the last settings you mentioned are, sorry...

VTT was 1.30V.

[Fritz_the_germ]

Ei horsch eh mol:
Unter dem Kapitel Clock Setting Fine Delay is to find DLL and RCOMP Seetings "By Menu" just down there "Ch1 DRAM Default Skew... Model 3, Ch2 DRAM Default Skew Model 3, RCOMP Setting Model 1.
How was your FSB Vref

[zsamz_]

fritz use the pulls its much easier

[Fritz_the_germ]

O.K. I will try so.
Is it possible to enable just a part of the Channel Phases (for example Channel 1 Phase 0 Pull-in until Channel 1 Phase 4 Pull-In on "enabled" and let Channel 2 Phase 0 until Phase 4 on "Auto") or do I have to enable all the Channels?
Is there a rule of a right combination?
I know one thing for sure: If a adjust all channels on "enabled" I will lower my PL for just one step.

[zsamz_]

O.K. I will try so.
Is it possible to enable just a part of the Channel Phases (for example Channel 1 Phase 0 Pull-in until Channel 1 Phase 4 Pull-In on "enabled" and let Channel 2 Phase 0 until Phase 4 on "Auto") or do I have to enable all the Channels?
I there a rule of a right combination?
I know one thing for sure: If a adjust all channels on "enabled" I will lower my PL for just one step.

no not all
i do
eaeee eaaee
it leaves it some breathin room
you wont see pl goin down in windows but it will be -1 pl
do an everest test an d you will see

[Fritz_the_germ]

Thank you for your advise. The data throughput on "read" is about 250 MB/s higher than having all Channels on "auto".
It workes really well:



But do you have something like a rule of thumb for adjusting the Channel 1 and 2 Phases auto or enabled. I want to understand what I am doing.

[angoholic]

@zsamz_

I did not try much channel fine tuning yet but did you test that at high fsb too? would do it but currently no DK to test there for me

[zsamz_]

@zsamz_

I did not try much channel fine tuning yet but did you test that at high fsb too? would do it but currently no DK to test there for me

did you kill all them boards?
i think i got her to around 500 with phases for pl7
i havent played with ddr2 since i got my rampage
my goal is pl6@500fsb+
i was primin @600fsb last week lol

fritz: see if you can run 5-4-4-9 @ that speed
and set your multi to x9
no rules on phases just tighten untill it doesnt boot or unstable lol
i always do eaeee or eaaee or eaaae
secong phase always a bit looser to give some breathing room

[Fritz_the_germ]

@zsamz_,
you tell me so because I am not even running my sticks on default, don´t you?
O.K. I will give it a try CL 5-4-4-9.

[zsamz_]

@zsamz_,
you tell me so because I am not even running my sticks on default, don´t you?
O.K. I will give it a try CL 5-4-4-9.

your gskills can do 1020mhz easy cas 4 and 1300 cas 5
test then 4-4-4-12-4-42 and 5-4-4-9-4-42 and see whats better forget 5-5-5-15 at that speed
btw when testin max clocks i always do a pass of test #5 with memtest iso before i even enter windows

[mikeyakame]

In my experience with pull-ins it normally goes like this.

eaaaa -> eaaae -> eaeae -> eaeee -> eeeee

ch2 should always have less pull ins at tight pl, also ch2 dll clock fine delay (which ever slot you are using) can be delayed within 15-20ps of ch1 if your memory can handle it. normally ch1 fine clock delay will be 30-40ps advanced of ch2.
so ie ch1 dll clk delay = 330ps, ch2 dll clk delay = 370ps, that is considered advanced.
so ie ch1 dll clk delay = 350ps, ch2 dll clk delay = 325ps, would be advancing ch2 and can make a slight improvement if the pull ins are setup with that in mind. something like ch1 = eeaae, ch2 = eaaee.
you can basically use both dll clk/control delays and phase pull-ins hand in hand if you don't mind doing a lot of adjust, test and repeat, and a full memory test each time before you boot windows so if there is any major problem it'll crash that instead of your OS install



it takes a little stress off the nb under load, and puts a little more on the memory subsystem, it helps when the nb clock gets a little skewed under high freq/heavy load because the memory clock delays on that channel will be a little more advanced.

[Fritz_the_germ]

Thank you Mike for your advise,
I am not sure if I got your recommanded combination right.
eaaaa(=CH1) -> eaaae (=Ch2) -> eaeae(=Ch1?) -> eaeee (=Ch2?)-> eeeee
Does it mean eaaaa should be for Channel 1 eaaae for Channel 2 and so on?

[PatRaceTin]

i have been try P45 T2RS PLUS and suffer from VDroop

i want to know P45 T3RSB PLUS have same VDroop??

thank you

[mikeyakame]

Thank you Mike for your advise,
I am not sure if I got your recommanded combination right.
eaaaa(=CH1) -> eaaae (=Ch2) -> eaeae(=Ch1?) -> eaeee (=Ch2?)-> eeeee
Does it mean eaaaa should be for Channel 1 eaaae for Channel 2 and so on?

Order of changing any channel, or at least that's what I recall it is. You cant just change 1 2 3 4 5, you need to alternate in a certain way between ch1 and ch2 and sometimes dll clk skews.

[Fritz_the_germ]

Yoh guys,
yoh Mike,
I have tried a lot of "Read Delay Phase Adjust" combinations.
Some of them worked, some of them caused bluescreens or C1 faults.
The one I am using right now is on Channel 1 eaeae combined with Channel 2 eaaae. That pushes the Read Delay Adjust +21T as you see below:



Using the combination CH1 eaaae Ch2 eaaae the Read Dealy gets pushed to +17T. That means as long as the combination is right the setting "enabled" instaed of "Auto will push +4T, right??
So far the easy thing.
Mikeyakame, you mentioned in your last post that "so ie ch1 dll clk delay = 330ps, ch2 dll clk delay = 370ps, that is considered advanced.
so ie ch1 dll clk delay = 350ps, ch2 dll clk delay = 325ps, would be advancing ch2 and can make a slight improvement if the pull ins are setup with that in mind. something like ch1 = eeaae, ch2 = eaaee".
Could you be so kind and give me a little more explaination to that part?

The fine Delay Step Degree shows me 70 ps by using the upper Read Delay Phase combination. The Ch1&Ch2 Clock Crossing Setting is both "nominal" the values below are:
DIMM 1 Clock fine delay...................Current 1924ps
DIMM 2 Clock fine delay...................Current 1924ps
Ch 1 Control0 fine delay..................Current 194ps
Ch 1 Control1 fine delay..................Current 194ps
Ch 1 Control2 fine delay..................Current 110ps
Ch 1 Control3 fine delay..................Current 96ps
Ch 1 Command fine delay...................Current 134ps

Ch2 Clock Crossing Setting................Nominal
DIMM 3 Clock fine delay...................Current 1924ps
DIMM 4 Clock fine delay...................Current 1882ps
Ch 2 Control0 fine delay..................Current 152ps
Ch 2 Control1 fine delay..................Current 152ps
Ch 2 Control2 fine delay..................Current 70ps
Ch 2 Control3 fine delay..................Current 56ps
Ch 2 Command fine delay...................Current 152ps

So where do I have to change the values to get "ch1 dll clk delay = 330ps, ch2 dll clk delay = 370ps, that is considered advanced.
so ie ch1 dll clk delay = 350ps, ch2 dll clk delay = 325ps" ?

I hope you don´t mind my penetrating curiosity but I am pretty amped to understand what my pc is doing when I´m adjusting "some letters".

[Fritz_the_germ]

Yoh guys,
what´s up? Is there anybody out there?
To bad that mikeyakame is still shooting kangaroos

[hawk999]

my 24/7 daily use



i just reached 4.1ghz too lazy to change the voltage ahhaha

[PaVi90]

hawk999: what memory do you use?

[hawk999]

Team Xtreem Dark 4gB ddr2-1066 5-5-5-15 @ 1.9v (stock volts)

[Theorw]

Does anyone know where i can find a LP DK X48 T2RS thread around here????
I happen to have one for some days and i d like to find some volt mods,measuring points etc...
ANY HELP???

Thanks in advance!

[hawk999]

@Theorw try this http://csd.dficlub.org/forum/index.php

[Fritz_the_germ]

Yoh guys!
Here is another oced Q9650@DFI DK P45-t2RS Plus:



And some Everest report:

[zsamz_]

fritz i'm gonna play with q9650 +dk can you post bios settings and wich bios you used

ty

[Fritz_the_germ]

Yoh zsamz_
here you go with the BIOS settings. I am using the latest beta (8.19)
Don´t forget the germans mention at first the day and then the month (19.08=german; 08/19 is english) Can you relay to that?

BIOS-Settings des DFI LANPARTY DK P45-T2RS Plus
BIOS v. 19.08.2009-D45PDA819
30.08.2009

CPU Feature Page
Thermal Management Control................Disabled
PPM (EIST) Mode............................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Execute Disable Bit.......................Disabled
Virtualization Technology.................Disabled
Core Multi-Processing.....................Enabled

Main BIOS Page
Exit Setup Shutdown......................Mode 2
Shutdown after AC loss....................Enabled
AC Shutdown free..........................Enabled
O.C. Fail Retry Counter...................1
O.C. Fail CMOS Reload.....................Disabled
CPU Clock Ratio........................... 8 x
CPU N/2 Ratio.............................Enabled
CPU Clock.................................495
Boot Up Clock.............................345
CPU Clock Amplitude....................... 700mV
CPU Clock0 Skew........................... 100ps
CPU Clock0 Skew........................... 100ps
DRAM Speed................................333/800=1190 MHz
PCIE Clock................................100MHz

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled

Voltage Setting Page
CPU VID Control......................... 100 mV
DRAM Voltage Control......................2.001 V
SB Core/CPU PLL Voltage...................1.55 V
NB Core Voltage...........................1.4075 V
CPU VTT Voltage...........................1.34 V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
CPU GTL 0/2 REF Volt......................0.67X
CPU GTL 1/3 REF Volt......................0.67X
North Bridge GTL REF Volt ................0.63X

FSB Vref.................................. 24

DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Disabled
Clock Setting Fine Delay..................

Flex Memory Mode..........................Auto
CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................5
Precharge Delay (tRAS)....................15
All Precharge to Act......................Auto
REF to ACT Delay (tRFC)...................60
Performance Level.........................8
Read Delay Phase Adjust...................Auto
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................Auto
Rank Write to Read (tWTR).................Auto
ACT to ACT Delay (tRRD)...................Auto
Read to Write Delay (tRDWR)...............Auto
Ranks Write to Write (tWRWR)..............Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................Auto
ALL PRE to Refresh........................Auto

Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

Clock Setting Fine Delay Page
DLL and RCOMP Settings .................ByMenu
Ch1 DRAM Default Skew.....................Model 3
Ch2 DRAM Default Skew.....................Model 3
RCOMP Setting.............................Model 1

Fine Delay Step Degree....................70ps


Ch1 Clock Crossing Setting................Nominal
DIMM 1 Clock fine delay...................Current 1924ps
DIMM 2 Clock fine delay...................Current 1924ps
Ch 1 Control0 fine delay..................Current 194ps
Ch 1 Control1 fine delay..................Current 194ps
Ch 1 Control2 fine delay..................Current 110ps
Ch 1 Control3 fine delay..................Current 96ps
Ch 1 Command fine delay...................Current 134ps

Ch2 Clock Crossing Setting................Nominal
DIMM 3 Clock fine delay...................Current 1924ps
DIMM 4 Clock fine delay...................Current 1882ps
Ch 2 Control0 fine delay..................Current 152ps
Ch 2 Control1 fine delay..................Current 152ps
Ch 2 Control2 fine delay..................Current 70ps
Ch 2 Control3 fine delay..................Current 56ps
Ch 2 Command fine delay...................Current 152ps

Ch1Ch2 CommonClock Setting................Nominal

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

Where the hell is mikeyakame? He hasn´t shown up for weeks. The last thing I`ve heard about him was he is going to hunt some kangaroos...

[zsamz_]

thanks fritz
hopefully i get some time soon