DFI LANparty DK P45-T2RS/T3RS (Intel P45) - News|Info|Results

[ViViD]

Subtimings & Fine Delays Also Data transmitting



the copy is bad i know...

WoW It's Fantastic M8
664 MHZ FSB 99% FSB OverClock Congrat Man

[zsamz_]

whats the best bios for the board please
i loaded bios 320 funny stuff lol
booted @ 512fsb .everest and cpuz tell me i'm @330
setfsb tells me i'm @ 512 i know i'm @ 330 cause of everest scores

[lawrywild]

I'm using D45PDC29, worked best for me, especially with 2:3 divider

[zsamz_]

i loosened timings like crazy n i cant get to 500fsb
i think the board dont like either of my 4870 cards i get blue screen
put in my 8800gt i think my board is a flake cant hit 475fsb stable
i can boot @ 500 but rofl
tried 812 to newest bios

[zsamz_]

damn board needs 67% gtl setting to be stable

[ViViD]

67 In Bios Is Default GTL Yes?

[zsamz_]

67 In Bios Is Default GTL Yes?

but my cpu needed less than 63% on my other dfi boards

[Fritz_the_germ]

Yoh guys,
I am running my system with the settings below.
My goal is to set the bios option enhance data transmitting from fast to turbo.
Every time I am changing from fast to turbo the computer takes a while to start and if the pc finally starts the multipler has been changed from 8.5 to 6.

The other question I have is how to change the tRFEs in the bios from 3120T to 16.838T. I know I could use memset vers. 4 to reach this goal but I want to understand the memory bios options. It was hard enough to get my head around all the other stuff in the bios.

BIOS v. 03.10.2008-D45PDA03


CPU Feature Page
Thermal Management Control................Enabled
PPM (EIST) Mode............................Ensabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Enabled
Execute Disable Bit.......................Disabled
Virtualization Technology.................Disabled
Core Multi-Processing.....................Enabled

Main BIOS Page
Exit Setup Shutdown......................Mode 2
Shutdown after AC loss....................Enabled
AC Shutdown free..........................Enabled
O.C. Fail Retry Counter...................1
O.C. Fail CMOS Reload.....................Disabled
CPU Clock Ratio........................... 8.5 x
CPU N/2 Ratio.............................Disabled
CPU Clock.................................470
Boot Up Clock.............................375
CPU Clock Amplitude....................... 800mV
CPU Clock0 Skew........................... 100ps
CPU Clock0 Skew........................... 100ps
DRAM Speed................................333/800=1129 MHz
PCIE Clock................................100MHz

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled

Voltage Setting Page
CPU VID Control........................ +100mV
DRAM Voltage Control......................1.95V
SB Core/CPU PLL Voltage...................1.55V
NB Core Voltage...........................1.295V
CPU VTT Voltage...........................1.25V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
CPU GTL 0/2 REF Volt......................0.67X
CPU GTL 1/3 REF Volt......................0.67X
North Bridge GTL REF Volt ................0.67X

FSB Vref.................................. Auto

DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Disabled
Clock Setting Fine Delay..................look in the list below.

Flex Memory Mode..........................Auto
CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................5
Precharge Delay (tRAS)....................15
All Precharge to Act......................6
REF to ACT Delay (tRFC)...................54
Performance Level.........................8
Read Delay Phase Adjust...................Auto
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................Auto
Rank Write to Read (tWTR).................Auto
ACT to ACT Delay (tRRD)...................Auto
Read to Write Delay (tRDWR)...............Auto
Ranks Write to Write (tWRWR)..............Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................Auto
ALL PRE to Refresh........................Auto

Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

Clock Setting Fine Delay Page
DLL and RCOMP Settings .................ByMenu
Ch1 DRAM Default Skew.....................Model 3
Ch2 DRAM Default Skew.....................Model 3
RCOMP Setting.............................Model 1

Fine Delay Step Degree....................70ps


Ch1 Clock Crossing Setting................Nominal
DIMM 1 Clock fine delay...................Current 1924ps
DIMM 2 Clock fine delay...................Current 1924ps
Ch 1 Control0 fine delay..................Current 194ps
Ch 1 Control1 fine delay..................Current 194ps
Ch 1 Control2 fine delay..................Current 110ps
Ch 1 Control3 fine delay..................Current 96ps
Ch 1 Command fine delay...................Current 134ps

Ch2 Clock Crossing Setting................Nominal
DIMM 3 Clock fine delay...................Current 1924ps
DIMM 4 Clock fine delay...................Current 1882ps
Ch 2 Control0 fine delay..................Current 152ps
Ch 2 Control1 fine delay..................Current 152ps
Ch 2 Control2 fine delay..................Current 70ps
Ch 2 Control3 fine delay..................Current 56ps
Ch 2 Command fine delay...................Current 152ps

Ch1Ch2 CommonClock Setting................Auto

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto


http://www.abload.de/img/timings-fast_fast1dqi.jpg

[mikeyakame]

You can't change tREF in bios. tREF of 16838T is far too long and will only cause memory corruption. The reason you get a drop in memory latency is because you are reducing memory subsystem bandwidth from overextending Self Refresh period. This is for benching only. It's not something you can use for every day. Enable all PL phase pull-ins and set PL to 1 higher. Your bios is pulling phases in on auto. See Read Delay Fine Adjust is +17T, that means Channel A PH1 + PH5 are both pulled in. PH1 = +1T, PH5 = +16T.

[Fritz_the_germ]

Thank you Mike,
would it be a great difference if I leave the Pl on 8?

[zsamz_]

i noticed if i dont set ALL PRE to Refresh to 8 on 500+fsb my fsb reverts to 333
anyone else get this?
fritz dont enable all pulls do eaeee eaaee
angoholic can you share bios setting for that nice cas4 run

[mikeyakame]

Well PL9 with all phase pull ins enabled is same as PL8

[radaja]

what is tREF and how does it affect memory performance?

[mikeyakame]

tREF is memory ic self refresh period. it's basically the turnaround for refreshing all blocks of memory. Basically self refresh goes through all addresses and checks if data is valid or not, if its valid it refreshes it, if its invalid it precharges it. It uses idle memory bandwidth, but setting its value to the maximum you can fit in the register, you decrease memory latency by 1-2ns at the cost of killing actual memory performance under heavy utilization (since you now need to fetch lost memory data through FSB instead of accessing locally) and risking losing data in memory. It's a benchmark hack nothing more nothing less.

The correct value is calculated by:

REF[T] = REFI[ns] / Ck[ns]; where REFI[ns] is Refresh Interval in NS of ICs (usually 7800ns / 7.8us) for performance memory, Ck[ns] is clock period of current frequency (1000/bus_frequency) bus_frequency is half DDR.

So usually at 1066mhz, tREF is 4171T. 4171T = 7800ns / 1.8666ns, where 1.8666ns is clock period at 1066mhz DDR, 1000/533.

The 16838T value mentioned is simply the largest value the tREF mchbar register can hold. its a 4bit register, so FFFFh is largest timing you can use.

[radaja]

ok thanks for the info.i dont ill mess with this.

[zsamz_]

16838T is too high even for a bench the odds of corrupting windows is high

[radaja]

has anyone ever had orthos blend have one core fall behind?im not talking 2 or 3 thread but
like this.im on fft 640 and core 1 is at thread6 and core 2 is at thread 2 of 512 fft

[SpuTnicK]

Does this mobo like quads? Anyone hit 500+fsb 24/7 with quads?
And can it work properly with 1200mhz 2x2gb memory?

[zsamz_]

Does this mobo like quads? Anyone hit 500+fsb 24/7 with quads?
And can it work properly with 1200mhz 2x2gb memory?

i gonna get a set of lv 9600 soon i did 1140 on my redline and 1300+ with d9
only weak point i see is running 4 sticks but my board is not as strong as the others ive seen
500fsb is no problem
but 4 sticks @ 1200mhz

[radaja]

i thought i read somewhere that dfi boards setup(optimized) for 2x2GB configuration.

[zsamz_]

i thought i read somewhere that dfi boards setup(optimized) for 2x2GB configuration.

dfi boards love 2x2 kits especially the x48
newest bios supports 16 gigs lol

[Fritz_the_germ]

@mikeyakame,
Yesterday, I enabled all the Channel Phases Pull-Ins running a Pl of 9 and Everest showed me the very same memory datas like I had with Phases Pull-In set on Auto running a Pl of 8.
Dear Mike, your knowledge about all that stuff is really legend
Later I tried to run all Phases Pull-Ins on enabled plus a Pl of 8 but my system refused to start. That means I could not run my system with all Phases Pull-Ins on Auto combined with a Pl of 7.

Looking back to the tFREs of my system the value of 4,399T should be the magic number (7800/(1000/564)= 4,399 isn´t it. That means I could change the tFREs with Memset vers. 4 to this value without causing memory instabilities, right?
But there is still another thing that really bothers me- I am having two sticks of the F2 9600 memory but with my settings right now I am running under the default speed. This board doesn´t have a 3:4 divider so I am not able to run a fsb of 460 MHz or higher combined with a high memory speed.
Do you have a recommandation -except reducing the fsb- to run a high memory speed plus a high fsb (460 Mhz or higher)?

[greg.m]

@mikeyakame,
Yesterday, I enabled all the Channel Phases Pull-Ins running a Pl of 9 and Everest showed me the very same memory datas like I had with Phases Pull-In set on Auto running a Pl of 8.
Dear Mike, your knowledge about all that stuff is really legend
Later I tried to run all Phases Pull-Ins on enabled plus a Pl of 8 but my system refused to start. That means I could not run my system with all Phases Pull-Ins on Auto combined with a Pl of 7.

Looking back to the tFREs of my system should the value of 4,399T be the magic number (7800/(1000/564)= 4,399 isn´t it. That means I could change the tFREs with Memset vers. 4 to this value without causing memory instabilities, right?
But there is still another thing that really bothers me- I am having two sticks of the F2 9600 memory but with my settings right now I am running under the default speed. This board doesn´t have a 3:4 divider so I am not able to run a fsb of 460 MHz or higher combined with a high memory speed.
Do you have a recommandation -except reducing the fsb- to run a high memory speed plus a high fsb (460 Mhz or higher)?

try to run higher than 500fsb

[mikeyakame]

@mikeyakame,
Yesterday, I enabled all the Channel Phases Pull-Ins running a Pl of 9 and Everest showed me the very same memory datas like I had with Phases Pull-In set on Auto running a Pl of 8.
Dear Mike, your knowledge about all that stuff is really legend
Later I tried to run all Phases Pull-Ins on enabled plus a Pl of 8 but my system refused to start. That means I could not run my system with all Phases Pull-Ins on Auto combined with a Pl of 7.

Looking back to the tFREs of my system should the value of 4,399T be the magic number (7800/(1000/564)= 4,399 isn´t it. That means I could change the tFREs with Memset vers. 4 to this value without causing memory instabilities, right?
But there is still another thing that really bothers me- I am having two sticks of the F2 9600 memory but with my settings right now I am running under the default speed. This board doesn´t have a 3:4 divider so I am not able to run a fsb of 460 MHz or higher combined with a high memory speed.
Do you have a recommandation -except reducing the fsb- to run a high memory speed plus a high fsb (460 Mhz or higher)?

Higher FSB you go the looser you need to go with PL.

www.jedec.org/download/search/JESD208.pdf

If you're interested in tREF (Self Refresh) and other memory info, take a read of that PDF I linked. It's Jedec DDR2-1066 standards. It's got a lot of really useful info and diagrams on the fundamentals. There should even be a section explaining what Self Refresh does and how it works.

There is no real performance gain from changing tREF so forget about it. It's just a method of self refreshing memory ics during idle clocks to improve bandwidth.

[Fritz_the_germ]

Thank you Mike,
your reply and your link is precisely what I ´ve been looking for.
I know this rule of a thump, the higher the fsb is the higher has to be the PL.