that's exactly what will happen. a new driver release fixes the issue. the rendering output is unchanged, so isnt that an acceptable solution?
it's basically a software based OCP that results in exactly the same what the canardpc author suggests "the regulator should warn the pilot that the limits of the components are about to be reached, resulting in a secure and automatic underclocking."
uh what evidence does he have for such an accusation? just wild guesswork? maybe he called fudo and asked for advice how to write a story.according to him, this defect is sure to have been detected in AMD's quality check process, but have been ignored on purpose. And he goes on by saying that the OCP mecanism is badly implemented, and that this is a true problem on those cards...
the ocp mechanism implementation is perfectly fine, it's just the ocp limit that is set too low.
i doubt the problem lies in 3 phase vs. 4 phase but ocp set too low vs. ocp set not too low. no data or evidence in the whole article, next please
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