Some speculation about that Larrabee die shot - techreport

[ajaidev]

http://www.techreport.com/discussions.x/16920

Bit interesting

[Manicdan]

this was posted in another LRB topic, not as the starter, but as a reply

[saaya]

Also, Larrabee cores are dual-issue capable, with a separate scalar execution unit.

i thought they are quad issue capable?

I'd assume we're looking at GDDR5 memory, which would mean four transfers per clock over that 256-bit (aggregate) memory interface.

i think larrabee will rather have a 512bit memory interface... why?

• the ringbus is 512bit bi-directional
• we are dealing with 32 x86 cores which are quad issue capable, quad hyper threadding pretty much
• intel wants to win the performance crown with brute hardware performance force, they have to, cause they are lacking efficiency and in their drivers, they arent stupid, they know they need more raw power to beat ati and nvidia
• intel has a very good integrated 192bit (3x64) and 128bit (2x64) memory controller in mass production on their i7 (i5) cpus in 45nm
• nvidia uses a 512bit memory controller in their current gen already
• doing a lot of the rendering in software will mean extra demand in bandwidth
• we know larrabee will be a rather big chip, very big, so theres more than enough room for a 512bit interface

so... wouldnt it make more sense to assume a 512bit memory controller? since its 4 blocks, probably 4x128?

I've got to think we're looking at somewhere between 1.5 and 2.5GHz.

it has been hinted from several sites already that the final clock will most likely be around 2ghz or higher

so from the hardware specs, larrabee at 2.5ghz is around 2x as fast as a GTX285 or 4890 card...
i dont think even intel would dare to claim they will be able to use the hardware as efficient as a conventional gpu... doing a lot in software will mean they are slowed down by a big overhead, especially internal bandwidth will really be busy i think...

then take into account that, roughly, by the time larrabee arrives we will have rv870 and gt300, and all the sudden larrabee doesnt look all that impressive anymore.

[saaya]

where is all this 600-700mm^2 for larrabee coming from?
look at the wafer and count and then divide 300mm by the number of chips from each side and you get around 13x22mm... thats 300mm^2, not 600 or even 700
http://www.dvhardware.net/news/intel...df_april09.jpg

thats only a tad bigger than G92b and rv770!
in that case, it definately looks like larrabee will be 256bit memory... it would cost too many transistors to get 512bit done...

on rv770 the 256bit gddr5 imc takes almost exactly 40x1mm of the die space, and on larrabee there are pads on the side of the die along the long sides of the chip, which are around 22mm each, so that gives intel roughly 44x1mm, it doesnt seem to use the far outer edges, so thats exactly 40x1mm then, perfect match...

rv770s pciE interface is around 10x1mm, on larrabee the left side is almost empty, no interface there, the right side features at least 2 of not 3 interfaces, the largest of it 6x1mm in size, which is probably the pciE interface. we are comparing 55nm with 45nm here after all, and a shrink to 60% of the 55nm dimensions makes sense.

this means though, that the gddr5 imc on larrabee should be more than 256bit... since the 45nm pciE interface looks to be 60% of the 55nm one, the 256bit gddr5 imc should be 28x.7mm... so how come its bigger? well, we are comparing intel vs tsmc here for one thing, so it might just be that... but i wouldnt be surprised if intel increased the imc to 384bits... that would be a 50% boost in bandwidth, something larrabee could definately use very well...

what really really confuses me is this: the left edge of the die is virtually left empty... which makes no sense to me...
they could have added another imc there, a qpi link... but... nothing... thats really odd imo...

and another thing, they didnt think ahead with their design... the way they arranged everything on the chip, they wont be able to easily double it up in 32nm or add more units to it. think about it... its a rectangular chip, but the imc is on top and bottom, the long sides, so they cant glue two pieces together there. they cant glue them together on the left side or right side either cause the resulting chip would be way way rectangular and would have very bad yields i suppose.
they cant just add more units either for the same reason... well, they can stretch it and make it a 40 unit design i guess, making it a very long stretched chip like atom, just much bigger... but beyond that they will have to tear every block apart and start again from scratch, not very smart... amd did it a lot better with K8 and K10 and intel followed up with c2d and i7.

this larrabee design looks very un-modular in contrast, and very un-upgradeable

[Manicdan]

wiki says 49x49mm, the screenshot also looks a bit off, weve seen square chips, and the layout of the 32 cores. sofar they are looking to be huge chips to get all 32 cores in there.

[saaya]

49x49? that doesnt make any sense, does any of the larrabee wafer or chip shots look square to you? thats bs information... maybe intel is spreading flase info on purpose to confuse ati and nvidia...

49x49 might be the 65nm 10core or 16core test chip... actually no, that still wouldnt make sense...
even a 32core 65nm chip should be smaller than that...

[trinibwoy]

i thought they are quad issue capable?

No there can be four threads active at once but you can only issue two instructions per clock - one to the scalar x86 core and another to the vector unit. Hence dual-issue.

[Manicdan]

heres a nice thread about its size http://www.nvnews.net/vbulletin/showthread.php?t=131332

the ones your seeing are probably a lower model with less cores, the 32 core one seems to be the 600mm2 one everyones talking about

[moose517]

alright sorry to sound a like a noob, but how can people teel what is what on a die? In the B3D thread they are labeling the different parts but all i see is different colors, how can you guys tell whats what on a die? just the color give it away or what?

[saaya]

heres a nice thread about its size http://www.nvnews.net/vbulletin/showthread.php?t=131332

the ones your seeing are probably a lower model with less cores, the 32 core one seems to be the 600mm2 one everyones talking about

hummm confusing... somesthing weird is going on here...

the dies on that wafer are ~23x30mm which is 690mm^2
and i cant make out any design on the wafer, it could be anything...
the dies on that wafer are rather square, the die that intel showed a huge res pic of was notably rectangular.

so there are either 2 versions of larrabee or one of them isnt larrabee

http://www.dvhardware.net/news/intel...df_april09.jpg
http://xs538.xs.to/xs538/09150/patspeech2790.jpg790.jpg

the first one HAS to be larrabee for sure, cause it looks exactly like the high res shot:
http://img13.imageshack.us/img13/3552/lrb21.jpg

the second one could be anything... now the interesting thing is this...
the smaller chip they showed actually appears to be a 32 core version of larrabee... so 32core larrabee is NOT 690mm^2.

could the smaller chip be an early 32nm shrink of larrabee then?
unlikely, you dont go from 690 to 300, thats too much of a shrink.
plus you wouldnt go from 30x23 to 23x13...
plus why would intel shrink the 32core version to 32nm without adding more cores? nah, thats rather unlikely...

could the larger die be a larger version of larrabee then?
thats all i can think of... either its not larrabee at all, or its a larger version of larrabee... the smaller chip is ~300mm^2, the larger version is ~700mm^2

so what? 64cores? 0_o

alright sorry to sound a like a noob, but how can people teel what is what on a die? In the B3D thread they are labeling the different parts but all i see is different colors, how can you guys tell whats what on a die? just the color give it away or what?

there are 3 diferent identical looking blocks, we know that the highest amount of blocks will be the cpu cores, everything else is pretty much following the other things we know already, hardware texturing etc...

[Shintai]

Hmm...I dont think pic 1 is Larrabee. its supposed to be from beijing. And this is Beijing.

http://download.intel.com/pressroom/...PatSpeech2.JPG

It looks to be...empty? 32nm 291Mbit SRAM? I cant remember

[rozzyroz]

what about their "stacking" methods talked about with the terascale project?

http://techresearch.intel.com/articl...Scale/1421.htm

i dont know, but i cant wait to see some non-3d apps ran on this beast ...

i mean i would like to see the 3d apps as well, but what has me interested is the other features/benefits larrabee will have.

[Manicdan]

the large picture showing the 32 cores is very square
the one you think is LRB thats smaller, is from the same demo that was mentioned in the thread i posted, to be the wrong core. sofar every source is showing off a large square die. there is only one exception of a smaller die, thats rectangular, which dosnt fit anything else mentioned.

and here is where i saw 49x49mm
http://arstechnica.com/hardware/news...ee-part-ii.ars

[Shintai]

the large picture showing the 32 cores is very square
the one you think is LRB thats smaller, is from the same demo that was mentioned in the thread i posted, to be the wrong core. sofar every source is showing off a large square die. there is only one exception of a smaller die, thats rectangular, which dosnt fit anything else mentioned.

and here is where i saw 49x49mm
http://arstechnica.com/hardware/news...ee-part-ii.ars

That 49*49 is from 2 years ago. There was no larrabee silicon at that time. Not even to mention the 16-24 cores

[_Lone_Wolf_]

49mm x 49mm refers to package size, not die size.

[saaya]

Hmm...I dont think pic 1 is Larrabee. its supposed to be from beijing. And this is Beijing.

http://download.intel.com/pressroom/...PatSpeech2.JPG

It looks to be...empty? 32nm 291Mbit SRAM? I cant remember

which of them?
the chip in the background is 300mm^2, the one is his hands is the 700mm^2 chip

300mm^2 chip in the background
http://download.intel.com/pressroom/...PatSpeech2.JPG
http://www.dvhardware.net/news/intel...df_april09.jpg

700mm^2 chip in his hands
http://download.intel.com/pressroom/...PatSpeech2.JPG
http://xs538.xs.to/xs538/09150/patspeech2790.jpg790.jpg

ok, so then the smaller rectangular chip is 32nm sram i guess?
it doesnt look like sram though... maybe its a 24core mainstream 32nm larrabee? the size and rectangular shape would fit if they remove one of the 3 rows...

the large picture showing the 32 cores is very square
the one you think is LRB thats smaller, is from the same demo that was mentioned in the thread i posted, to be the wrong core. sofar every source is showing off a large square die. there is only one exception of a smaller die, thats rectangular, which dosnt fit anything else mentioned.

and here is where i saw 49x49mm
http://arstechnica.com/hardware/news...ee-part-ii.ars

thats the package size, not the chip size
but thanks, that at least clears up the 49mm thing then

[Shintai]

The 49x49mm is still a random homemade board design....

[marten_larsson]

If 49x49mm would have been the die it would be 2401mm², probably the most expensive graphics card ever to be produced!

[Hornet331]

^^ bigger then mcm power5

[saaya]

The 49x49mm is still a random homemade board design....

afaik its not, but who cares? who cares what the package size or amount of pins is going to be...