AMD embraces AVX making a new superset with SSE5(256bit support)

[informal]

Well this blog post from Mr. Dave Christie is really shedding more light into the whole SSE5/AVX confusion.

A few key points we can get from reading his post(and these do make my topic title vaild,ie. it IS a SUPERSET since AMD will support BOTH AVX and their own XOP extensions!):

1) AMD will support AVX instr. set extension while adding its OWN extension set named XOP.CVT16 and FMA4.

Quote from Mr. Christie's post :

This week, AMD is making a couple of very important announcements for developers: support of Intel's Advanced Vector Extensions (AVX) instruction set in future AMD processors, and the adaptation to the AVX framework of AMD's previous SSE5 instruction set proposal. The latter step has resulted in three new extensions: XOP (for eXtended Operations), CVT16 (half-precision floating point converts), and FMA4 (four-operand Fused Multiply/Add). In this posting I'll give an overview of the capabilities that these extensions provide, and also some insight into why we're taking this step.

With this duplication of functionality between SSE5 and AVX/FMA, and AVX's additional features, [B]we felt the right thing to do was to support AVX.[/B] In our minds, a more unified instruction set is clearly what's best for developers and the x86 software industry. With our acceptance of AVX, a key aspect of this instruction set unification is the stability of the specification. Since we don't control the definition of AVX, all we can say for sure is that we expect our initial products to be compatible with version 5 of the specification (the most recent one, as of this writing, published in January of 2009), except for the FMA instructions, which we expect will be compatible with version 3 (published in August of 2008).

FMA differences:

Why the FMA difference? This was not something we did lightly. In December of 2008, Intel made significant changes to the FMA definition, which we found we could not accommodate without unacceptable risk to our product schedules. Yet we did not want to deprive customers of the significant performance benefits of FMA. So we decided to stick with the earlier definition, renaming it FMA4 (for four-operand FMA - Intel's newer definition uses what we believe to be a less capable three-operand, destructive-destination format). It will have a different CPUID feature flag from Intel's FMA extension. At some future point, we will likely adopt Intel's newer FMA definition as well, coexisting with FMA4. But as you might imagine, we may wait until we're sure the specification is stable.

Additional value through added previous SSE5 instructions into the AVX spec. thus giving BD cores some more functionality:

The fact remains that AVX does not incorporate all of SSE5's features. Since SSE5 was based on months of discussions with ISVs on what sort of capabilities they felt were needed, and had been positively reviewed by the industry when we first put out the specification, we decided to follow through with development of these additional features. To do so most effectively, we redefined them in the AVX framework, resulting in the XOP extension.

2) as a natural consequence of 1)-full AVX support ,AMD must support 256bit wide SSE2/3/4.. instruction set extensions too. This means BD cores will have a superset of full AVX inst. set extensions PLUS an AVX-adopted (previous SSE5) XOP,CVT16 and FMA4 extension sets!

This is very important bit of news. The blog post by senior architect tells us that AMD is embracing the AVX spec. AND incorporating their new SSE5 additional instructions into the AVX-like decoding scheme.The only difference is the FMA extensions which Sandy Bridge will lack anyway and BD cores can't change since it would significantly alter the time to market of AMD's future new gen. uarchitecture.


So Superset stays and was 100% on the money



EDIT:

A few comments from AMD's industry partners that emphasize the importance of AVX support and of a new superset that AMD created:

Absoft
"The addition of AVX support by AMD is a great move as it enables superior performance potential across AMD's x86 family of processors," said Wood Lotz, Absoft CEO. "AMD's use of AVX can also simplify development of high performance compilers and tools for companies like Absoft, and enable customers across a wide variety of industries to build faster applications."

Acumem
"Acumem fully supports AMD's adoption and enhancement of the AVX instructions and will follow this standard as it becomes available in the market. As an ISV for performance tools we clearly see potential for performance improvements with these new additions" said Mats Nilsson, VP Software Engineering at Acumem.

Axceleon
"Axceleon applauds AMDs efforts to support both specifications, AVX and SSE5, in their XOP specification proposal. The further enhancements in FMA4 which accelerate floating point algorithms are very important to Axceleon's HPC customers and will be welcomed across the board" said Mike Duffy, CEO of Axceleon.

Bibble Labs
"We at Bibble Labs are constantly looking for performance improvements, and as such we are investigating AVX because of the possible performance advantage it might bring. We also appreciate that AMD is taking an active role to ensure the instruction sets converge and not create separate, conflicting instruction sets," said Jeff Stephens, Vice President of Product Development, Bibble Labs.

Cakewalk
"We commend AMD for taking an active role in open standards, by unifying the x86 instruction set and merging SSE5 into the AVX specification. This can help improve compatibility and simplify the work for developers implementing this. We look forward to investigating AVX for potential advantages it may bring to our real-time applications and plug-ins," said Noel Borthwick, Chief Technology Officer, Cakewalk.

Nero
"We are pleased that AMD has decided to adopt the AVX instruction set extension instead of offering a variant," said Simone Hoefer, General Manager, Technology at Nero AG. "This will help reduce implementation complexity and multiple code-paths. We are confident that the SIMD (SSE/SSE2) optimizations already implemented will scale nicely to 256-bit/AVX, allowing us to truly embrace this new development."

Smith Micro Software
"Having to choose acceleration solutions that work well on both AMD and Intel CPU platforms, Smith Micro welcomes convergence of the x86 instruction set. AMD supporting AVX is desirable from Smith Micro's point of view," said Uli Klumpp, director of engineering, Smith Micro Software, Inc. "The AVX instruction set extensions are looking promising for further optimizing our computationally most demanding software, DCC and data compression products such as Poser and StuffIt."

Sonic Solutions
"AMD's adoption of AVX will help Sonic unify some of its engineering efforts and reduce development costs," said Jim Roth, Chief Technical Officer, Sonic Solutions. "We welcome this initiative and the proposed enhancements to the x86 processor architecture, which we will leverage to increase the responsiveness and performance of our digital media applications."

[v_rr]

Wasn't AMD going to create a new extension to X86 with purpose of the Fusion?
Like new instructions that run on GPU.

[informal]

So Shintai what's your comment on this new development? What happened with your "superset busting"?

[Trunks]

So Shintai what's your comment on this new development? What happened with your "superset busting"?

*cough* marketing tool *cough*

there you go

[Shintai]

So Shintai what's your comment on this new development? What happened with your "superset busting"?

You ate marketing as usual. Forgot the game and ran away with the ball.

Its still not a superset, its still not fully support. Its a partial support packed in some nice marketing words.

I think you mix AVX alike instructions with being support. They dont even support the same FMA do they?

At some future point, we will likely adopt Intel's newer FMA definition as well

Since we don't control the definition of AVX, all we can say for sure is that we expect our initial products to be compatible with version 5 of the specification (the most recent one, as of this writing, published in January of 2009), except for the FMA instructions, which we expect will be compatible with version 3 (published in August of 2008).

Compatible with something Intel will never release? LOL!