AMD embraces AVX making a new superset with SSE5(256bit support)

[kl0012]

Chad ,Mr Fog writes optimization manuals for intel hardware,I think he knows "a bit better" how things stand in AVX land than you do . Not only him,but several Ace's members stated the new specification was released just in time to beat AMD's release of their new instruction set extension . And AMD did change their drex decoding scheme just to embrace the previous VEX decoding that was the basis of previous AVX revision.

It amazes me how far will you go in intel's defense. Are you their lawyer, spokesperson or what?

EDIT:
I have found the original and revised AVX specs.
Original is here. It was valid until January 2009. Intel released a new specification 4 months ago(roughly) and here is the new pdf covering the revised AVX instr. set specification. I'm not aware if there are more revisions,maybe there are.

Also note that intel has stated that they won't have FMA(the crucial instruction update) in Sandy Bridge while AMD on the other hand had FMA even in their first SSE5 extension set! This means SB will lack one of the strong features BD will have.

1. It is really doesn't mather why & when Intel changed his spec for FMA instructions - AMD's decoding scheme is similar but isn't compatable to Intel's decoding scheme. Intel's AVX extends many of SSE2/3/4 instructions to 256bit 3-operands mode and that feature is missing from AMD's new instruction set.

2. Changes made by Intel to FMA instructions (4-operand => 3 operand) nothing more then simplifying CPU hardware. If AMD can implement 4-operand instructions then it is very easy to convert such instructions to 3-operand (it is supported by default).