Deneb just around the corner?

[Rammsteiner]

plus amd has been doing this for awhile(memory controller, hyper transport) and i think i7 might have a few glitches a bugs.

Hmmm, not so sure.

It's certainly true that AMD has like the 'experience' with HT and IMC's after those years of using it. So the chance for AMD to mess something up around either of those is very small, and with every new stepping/core/platform the chance becomes a lot smaller.

On the otherhand, HT and IMC's ain't like a secret thing. Ive no clue how it's build in, how it's different from MC's on the motherboard etc. I think the main issue for making that step is chosing the right moment. For example, Intel would have been stupid to do something like this while they were in the middle of X38 days and simply have mixed systems etc. It takes a complete new platform to introduce both HT/QPI and IMC's. It's possible Intel has some bugs and flaws in its design, but to be honest, that chance is pretty small since MC's in general are only having a risk of flaws when a new memory type is being used for the first time (DDR2, DDR3 etc). And HT/QPI, I dont think that's such a miracle thing. As said, it takes the right moment and of course a bit of engineering, but in the end it's just about optimizing FSB, or making it more efficient, mainly because 7 years ago we wouldnt even need such bandwiths.

Just my guess though

[Nedjo]

It's possible Intel has some bugs and flaws in its design, but to be honest, that chance is pretty small since MC's in general are only having a risk of flaws when a new memory type is being used for the first time (DDR2, DDR3 etc). And HT/QPI, I dont think that's such a miracle thing.

Well one thing is curious... ATM only two QPI controllers work in Nehalem... thus why 4/8-way Nehalem solution is scheduled for Q3 2009...

With HT AMD had fully working 4/8-way solution from day one!

[Jazzman]

On the otherhand, HT and IMC's ain't like a secret thing. Ive no clue how it's build in, how it's different from MC's on the motherboard etc. I think the main issue for making that step is chosing the right moment. For example, Intel would have been stupid to do something like this while they were in the middle of X38 days and simply have mixed systems etc. It takes a complete new platform to introduce both HT/QPI and IMC's. It's possible Intel has some bugs and flaws in its design, but to be honest, that chance is pretty small since MC's in general are only having a risk of flaws when a new memory type is being used for the first time (DDR2, DDR3 etc). And HT/QPI, I dont think that's such a miracle thing. As said, it takes the right moment and of course a bit of engineering, but in the end it's just about optimizing FSB, or making it more efficient, mainly because 7 years ago we wouldnt even need such bandwiths.

Just my guess though

Based on Nehalem overclocking results in some reviews, I think it does have some design flaws/inefficiency that causes 80C to 100C temps. Maybe it's the hardware or microcode but it definitely appears to be an issue.

Being a newbie with AMD, my understanding of AMD history is poor. I seem to recall that early AMD chips had very high temp problems when overclocked. Could be Intel has to go through the same pain for a while?

Demonkevy666 posted this url about the Nehalem temp issue on the other Deneb thread: HERE