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  1. #11
    Xtreme Mentor
    Join Date
    Aug 2008
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    I have been doing some testing on my Maximus II Formula (very similar to the P5Q-Deluxe) with Static Read Control & Dram Read Training enabled, and Clock Twister on Strong or Stronger. With Clock Twister set to strong/stronger it takes quite a bit of vNB to stabilize it, I was around 1.37 - 1.45 vNB for the various tests.

    The use of SRC & DRT and setting strong or stronger gives a definite boost to bandwidth across the board and reduces latency significantly. At 534 FSB 5:6 Divider I had to drop CT to Strong, as even with 1.49 vNB I could not get into windows. Also notice the latency is almost identical between 500 FSB 5:6 CT Stronger and 534 FSB 5:6 CT Strong.

    It appears that Clock Twister lowers latency significantly and has a noticeable but not large effect on bandwidth, and tRD (PL) has a great effect on bandwidth and a moderate effect on latency.

    OK anyone using the 266 strap, consider this. I was at:

    1112 MHz ram
    5-5-5-12-3-30-6-3 @ 2.00v
    PL8
    266 strap
    static read and dram read training disabled
    Clock twister on moderate
    vNB 1.27

    I was pulling ~9500MB/s & 54.5ns in everest



    I now have changed this to:

    1069MHz ram (1068 real)
    5-5-4-12-2-25-4-2 @ 1.94v
    PL8
    333 strap
    static read and dram read training enabled
    Clock twister on stronger
    vNB 1.30v **Using Clock Twister 'stronger' at this setting needs 1.30 vNB (compared to 1.27v) for stability due to aggressive chipset timings, I stopped dual windows memtest at 1500% coverage, which I consider to be stable. I can pass Orthos small and large FFT's and Linpack as well.

    and I get 60mb/s lower read bandwidth, the same write & higher copy bandwidth and 53.9 ns latency.



    Here is some further testing, notice the performance increase from using the more aggressive chipset timings. I highly recommend using Clock Twister 'Stronger', and enabling Static Read Control and Dram Read Training, as the bandwidth increase and drop in latency is remarkable, although still not as efficient as the P35/X38/X48 chipsets.

    450 FSB 3:4 Divider, PL8, SRC & DRT Enabled, CT Stronger:


    450 FSB 3:4 Divider, PL7, SRC & DRT Enabled, CT Stronger:


    500 FSB 5:6 Divider, PL8, SRC & DRT Enabled, CT Stronger:


    534 FSB 5:6 Divider, PL8, SRC & DRT Enabled, CT Strong:
    Last edited by CryptiK; 10-27-2008 at 03:39 AM.
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