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Thread: How to set up GTL Ref Values for 45nm & 65nm

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  1. #11
    Xtreme Member
    Join Date
    Dec 2006
    Location
    Germany
    Posts
    215

    Back from the testing front

    Hello,

    I did some tweaking last weekend and the result is rather interesting.

    My ASUS P5Q3 Deluxe board and a Q9300 C1 processor was previously set to the following, 7 hours Orthos stable:

    FSB: 460
    GTL ref 0/2: 0.69x
    GTL ref 1/3: 0.67x
    NB GTL ref: AUTO

    At this old configuration, the CPU GTL references have been extremely sensitive to what value I was setting. Give or take 0.02 and I got Orthos errors pretty quickly.

    Then I tried setting the NB GTL reference manually since I realized it's importance through this thread.

    New config:

    FSB: 460
    CPU GTL ref. 0/2: 0.63x
    CPU GTL ref. 1/3: 0.63x
    NB GTL ref: 0.68x

    The new thing is that the manual GTL setting allows for a FAR wider range of CPU GTL references. 0.69/0.67 still work fine but I can easily go down to 0.63 now while previously 0.665 was failing.

    I haven't tried just how far I can go, mostly because I feel a lot more comfortable with the once again decreased sentitivity of my system, which already goes beyond what I had on the Maximus Formula board.

    One observation with NB GTL on AUTO was that like, as soon as you would increase or decrease one of the CPU GTL references by 0.01, the respective other die would start erroring out as compared to the previous attempt. overall very random looking. It is also interesting that with NB GTL @ AUTO the 0/2 ref. neededto be higher than the 0/2 reference, which is very much against the BIOS' default which is 0.63 for 0/2 and 0.67 for 1/3.

    Also, the default value of 0.63x for the NB GTL doesn't work stable here, you have to go to about 0.68.

    All of this unfortunately doesn't help with the board's FSB wall at around 470. Neither does the needed CPU core voltage decrease through te changed NB GTL ref.

    ^.^Maybe that info is useful!

    I hope to replace my Q9300 C1 with a 9550 E0 next week. More testing coming up then!



    PS: Currently trying to reduce the FSB term. voltage. There is not much space tho, if I am staying above the core voltage.
    Last edited by Amurtigress; 10-22-2008 at 09:03 AM.

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