How to set up GTL Ref Values for 45nm & 65nm

[DemonEyez]

I was wondering the same thing. I think some one here will tell us but, I think it might be a little lower actually.. Correct me of wrong of course.

I was wondering, for CPU GTL Ref voltage the ideal range is between 0.80v and 1.005v as was stated earlier in this topic.
But what's the ideal range for the NB GTL Ref voltage? I get the impression that it's lower than CPU GTL Ref voltage because most of the time is has to be set with a (much) lower multplier (e.g. 65/65/63 or 63/63/58) Is this assumption correct?

[QUOTE=mikeyakame;3353927]ideal nb gtlref for standard Intel values is 0.666x vTT, but there is an extra value for the NB called FSB_SWING which is 0.25x vTT nominal, this is set by the manufacturer and it determines the distance for logical 0 / 1 from gtl ref voltage. it's the swing distance for a switched voltage. It may be that this is based off a divider from the GTLREF NB voltage which has already been reduced by a set of 1% resistors, it would make sense to do something along these lines as too high a vTT would cause too large swing between ground and power, perhaps thats the reason why we use smaller NB GTLREF multipliers or values.

[vox]

[QUOTE=DemonEyez;3361691]

ideal nb gtlref for standard Intel values is 0.666x vTT, but there is an extra value for the NB called FSB_SWING which is 0.25x vTT nominal, this is set by the manufacturer and it determines the distance for logical 0 / 1 from gtl ref voltage. it's the swing distance for a switched voltage. It may be that this is based off a divider from the GTLREF NB voltage which has already been reduced by a set of 1% resistors, it would make sense to do something along these lines as too high a vTT would cause too large swing between ground and power, perhaps thats the reason why we use smaller NB GTLREF multipliers or values.

ok so NB gtl ref, as a optimal range of variation from 0.641-0.689? (0.666 -+ 0.025) x vTT= value to put on the NB GTL Ref field??

[mikeyakame]

[QUOTE=vox;3361757]

[I]

ok so NB gtl ref, as a optimal range of variation from 0.641-0.689? (0.666 -+ 0.025) x vTT= value to put on the NB GTL Ref field??

optimal nb gtl reference voltage, as with optimal cpu gtl reference are only relevant to optimal clock drive amplitudes for optimal clock steps. to understand what I mean by this all you need to know is this...

pci clock amplitude is driven with roughly 100mv which is in respect to it working best either side of a 33mhz step, nb clock (fsb) amplitude is driven with roughly 200mv working best either side of a 66mhz step, dram clock amplitude is driven with roughly 400mv working best either side of a 133mhz step, and lastely cpu clock amplitude is driven with roughly 800mv working best either side of a 266mhz step.

what all this means is when changing the frequency for any of the particular bus' is that if you stick to a window of say 25% either side of that bus' tuned frequency steps, ie for a fsb frequency, 15-20mhz either side of lets say 400mhz base clock (stepped at 66mhz to prevent cross talk with other bus') , 380 - 420mhz will give you the best performance and require the least amount of variance from optimal settings, and most of the time provided the vTT is set to a reasonable enough voltage for your vcc and vnb voltages, then you will find that you can work with 0.63-0.65x for cpu gtl ref, and 0.60-0.63x for nb gtl ref.

it's only when you go outside these boundaries you will find the need to use radical gtl reference, fsb termination voltage, and cpu phase locked loop voltage (pll) to stabilize the system properly. certain fsb frequencies are no go zones unless you have clock drive amplitude adjustment, and even with this you have to set the drive amplitude for the nominal frequency steps you require to shield the fsb clock waves from other external bus clock waves, ie 433mhz or 499mhz fsb drop you smack on with the pci bus clock steps (every other 33mhz step, ie 33mhz, 99mhz, 167mhz, 233mhz, 297mhz and so on..)...all this means is without changing the amplitude the fsb clock is driven at and simply changing the frequency within 10-15mhz of these bands will always wreak system havoc at worst or need ridiculous amounts of extra voltage supply to the nb / cpu and way out gtl references to stabilize the system. if you obey the window either side of each 66mhz step, you will find the system performs better, is more responsive and most importantly you don't need to fully understand the concepts behind the design to make even minor adjustments, just a concept of tuned performance zones and basics of why you change the values and when you might need to change them.

[davidk21770]

[QUOTE=mikeyakame;3361904]

...you require to shield the fsb clock waves from other external bus clock waves, ie 433mhz or 499mhz fsb drop you smack on with the pci bus clock steps...

A few questions...

1. The quoted part of your statement seems to belie your signature's 1st CPU (the RF at 434).

2. I've had a heck of a time getting 430 stable -- which is close to 433. I was planning to keep working up in 5 MHz steps. Are you suggesting that I should jump to 440 or even 445 to get away from the 433 clock harmonic?

(PS... found the CPU PLL Voltage on my DFI. I just didn't read the whole SB voltage line... d'oh. Was really surprised that I didn't have it on the tweaker's nightmare 'er... paradise ).

[mikeyakame]

[QUOTE=davidk21770;3362295]

A few questions...

1. The quoted part of your statement seems to belie your signature's 1st CPU (the RF at 434).

2. I've had a heck of a time getting 430 stable -- which is close to 433. I was planning to keep working up in 5 MHz steps. Are you suggesting that I should jump to 440 or even 445 to get away from the 433 clock harmonic?

(PS... found the CPU PLL Voltage on my DFI. I just didn't read the whole SB voltage line... d'oh. Was really surprised that I didn't have it on the tweaker's nightmare 'er... paradise ).

yeah i ended up using 431mhz fsb to stabilize that overclock and way too much compensation adjustment across the board to get it working comfortably.

ended up using 112mhz pci-e to prevent the nvidia pll clock signal on my gpu leaking into my cpu clock signal! lol it took me a couple of weeks to figure out that was the actual problem and even that was an accident. i was looking over the gpu's memory register dump to try and make sense of memory timing setting DWORD's in the bios for the unknowns and noticed the pll deviation for i think it was the shader clocks.

long story short I gave up and dropped to 431MHz it was manageable to get working as long as I isolated SBPLL from CPUPLL. I ended up using 1.76v CPUPLL and 1.65v SBPLL to work around the cross chatter between the NB and SB. It was a work around really, and performance was never consistent, i'd get variations of 5 - 10 gigaflops at times through 5 or 6 problems in linpack, during the same run.

i finished up last night stability testing my new settings I wanted to try out, and only took 2 or 3 reboots to make small adjustments to vtt and nb/cpu gtlref to pass 1hr of prime95 before i stopped it and crashed out.

the end result is 474mhz fsb on 12:10 divider, common PL of 7 with CHA PH1 pulled in to 6, 3318mhz cpu 7x multi 1.34v vcc, 1.55v vnb, 1.58v cpupll, 1.50v sbpll, 1.075v vsb, 1.36v vtt, cpu gtlref 0.65x, nb gtlref 0.63x, rest arent all that interesting.

performance is quite good with 3.32ghz and cache/memory latencies are better than I expected from only using 1140mhz 5-5-5-15 on ram. memory latency is down around 52.3ns with 9700 / 8600 / 9500 read / write / copy bandwidths.

[vox]

[QUOTE=mikeyakame;3363387]

yeah i ended up using 431mhz fsb to stabilize that overclock and way too much compensation adjustment across the board to get it working comfortably.

ended up using 112mhz pci-e to prevent the nvidia pll clock signal on my gpu leaking into my cpu clock signal! lol it took me a couple of weeks to figure out that was the actual problem and even that was an accident. i was looking over the gpu's memory register dump to try and make sense of memory timing setting DWORD's in the bios for the unknowns and noticed the pll deviation for i think it was the shader clocks.

Hello mike!

So can we say that there is a relation bettewen the PCIE Frequency and the
FSB Strap To North Bridge???

ie: fsb to nb = 431 so pcie freq= 112
or fsb to nb= 466 so pcie freq=101????

if so how do we calculate it for varios values?

tks
vox

[mikeyakame]

[QUOTE=vox;3363500]

Hello mike!

So can we say that there is a relation bettewen the PCIE Frequency and the
FSB Strap To North Bridge???

ie: fsb to nb = 431 so pcie freq= 112
or fsb to nb= 466 so pcie freq=101????

if so how do we calculate it for varios values?

tks
vox

there is no way to calculate those kind of values. i used 112mhz for pci-e at 431 because it was the only frequency that in hd tune pro didn't appear to have erratic spikes in hard drive read speeds or access, also my gpu didnt magically drop the display out of nowhere while my system was idle.

avoid changing pci-e if you can unless you can say for certain the rest of the system is stable. at least if anomalies appear its a matter of making minor adjustments to the southbridge core voltage or sb pll voltage, if you do change sb pll voltage, change the cpu pll voltage by the same amount more to maintain the gap mainboard engineers design into the system to isolate each pll from the other and vice versa.

changing the pci-e freq more than 5mhz can wreak havoc if devices on the pci-e or southbridge don't tolerate more than a few mhz deviation from the 100mhz base clock. some hard drives will drop off the bus randomly or corrupt data if their controllers design can't work with more than 104-105mhz.

[truehighroller]

[QUOTE=DemonEyez;3361691]

ideal nb gtlref for standard Intel values is 0.666x vTT, but there is an extra value for the NB called FSB_SWING which is 0.25x vTT nominal, this is set by the manufacturer and it determines the distance for logical 0 / 1 from gtl ref voltage. it's the swing distance for a switched voltage. It may be that this is based off a divider from the GTLREF NB voltage which has already been reduced by a set of 1% resistors, it would make sense to do something along these lines as too high a vTT would cause too large swing between ground and power, perhaps thats the reason why we use smaller NB GTLREF multipliers or values.

Ok so, "0.666x vTT" is the standard right? In other words mine would be .666 x VFSB, which is 1.22 which would equal .8152 right? If so then I should make my 1.30 NBv x the ref for it equal, .8152 which would be, .63~ right? So in other words my gtl ref for the nb should be set to whatever multiplier, multiplied by 1.30 which is my NB voltage that gets me closest to the .8152? All the mumbo jumbo is not needed for me just the math in layman's terms will suffice.

[DemonEyez]

[I]

Ok so, "0.666x vTT" is the standard right? In other words mine would be .666 x VFSB, which is 1.22 which would equal .8152 right? If so then I should make my 1.30 NBv x the ref for it equal, .8152 which would be, .63~ right? So in other words my gtl ref for the nb should be set to whatever multiplier, multiplied by 1.30 which is my NB voltage that gets me closest to the .8152? All the mumbo jumbo is not needed for me just the math in layman's terms will suffice.

No, you make two errors. You can't calculate NB GTL Ref the same way as CPU GTL Ref.
Just like the CPU GTL Ref voltage, the NB GTL Ref voltage is derived from vTT.
Your calculation is flawed because you calculate as follows:

GTL Increment (in your examle .63) x vNB ( in your example 1.30v) = GTL Ref voltage 0.8152.

So in you calculation NB GTL Ref is derived from vNB and not vTT, that's error one.

Error two is that you asume the GTL Ref voltage needs to be 0.8152v.
For CPU GTL Ref voltage you would be correct, but for NB GTL Ref voltage there one problem:

but there is an extra value for the NB called FSB_SWING which is 0.25x vTT nominal, this is set by the manufacturer and it determines the distance for logical 0 / 1 from gtl ref voltage. it's the swing distance for a switched voltage. It may be that this is based off a divider from the GTLREF NB voltage which has already been reduced by a set of 1% resistors,

So in short, you have to take account for FSB_Swing and with your equation you do not.

Because it's unclear what the ideal range is and how it's calculated, i'm afraid it's trial and error.
A good starting point would be to asume that NB GTL Ref Voltage range has to be set lower than the CPU GTL Ref voltage range.
For 500FSB 1.30vTT and 1.41vNB setting NB GTL to 0.61x works best for me and
for 600FSB 1.36vTT and 1.45vNB setting NB GTL to 0.58x works best

I hope I explained it clearly for you.

If i made an error in my explanation please tell me so. It's just my interpretation of the info provided by Mikeyakame