Nehalem-EP......BLOOMFIELD

[Shintai]

But wouldn't have to raise the Timings (higher latency) for two channels of DDR-2000? Wouldn't this negate some of the extra bandwidth (performance wise)?

The cache and prefetchers makes memory latency almost irrelevant.

[Shadowmage]

The cache and prefetchers makes memory latency almost irrelevant.

That's 100% not true.... everything in addition to an in-order, simple pipeline is to combat memory latency. That's the whole purpose of out-of-order pipelines: to find work to do while waiting for a load to return.


EDIT: To prevent people from nitpicking me: yes, OoO processing was first invented by Tomasulo at IBM to combat long FP latencies, but now load instructions are the main reason why OoO is still mainstream. If you have ever designed an OoO processor, you would know that the overhead is massive compared to a nice and simple in-order processor.

[FlanK3r]

Ideal server CPU and for MTH