there are a few subtimings which can help a lot when you hit an error wall. tRTPD, tPTP, tRRD, tWTPD, tAPTRD, tAPTAD.
tRTPD (read to pre delay) add min +2 above value of tRP on 2gb sticks.
{
tAPTRD (all pre to ref delay) use tRTP + 2 (read to precharge)
tAPTAD (all pre to act delay) use tRTP + 2 (read to precharge)
} this is because you need to issue the command to all banks on same rank, you allow an extra clock to make sure they all receive the command, which is where the 2 comes from.
tRRD (act to act delay) basically you need to allow a slightly longer delay to ensure that when issuing a consecutive activate command that you allow at least enough time that the first activate command has arrived before activating another bank on the same rank, reason being that with four ranks you have double the amount of banks on each dimm and the chance of collisions on the bus becomes alot greater in a row cycle.
tWTPD (write to pre delay) little more time to complete write strobes usually results in lower latency and less errors / slowdowns, 14 - 16 are fine.
tPTP (pre to pre delay same rank) default is 1, which is ridiculously tight and i've seen it cause random errors at higher dram frequencies on certain IC's. 3 is the highest you can set, 2 is a good value for cautiousness. I havent in my experience found a value of 3 to be beneficial or help with errors at that point.
tRFC (refresh cycle turnaround) max turnaround between any two refresh commands. 8 bank / 4 rank sticks need at least 1.7x the amount of clocks for turnaround than the equivalent 4 bank / 2 rank sticks. Check JEDEC specs for DDR2-1066 and you will understand further. 1066 requires a minimum of 105ns for tRFC with 8 bank/4 rank due to FBAW (four bank active window) command turnaround (minimum time it takes for four banks active on any rank to complete their cycle which adds quite a large clock latency to ensure that any further activates dont collide or queue up and slow down bus traffic. 2 bank / 4 rank (256x4) 1gb sticks dont use FBAW so they can complete a refresh cycle alot more quickly, minimum for them is 54 or 56ns.
At 1066mhz CL5, tCK (clock period) is 533 / 5 (data freq / cas latency), 1.86ns. So to get tRFC from 105ns at 1066mhz, you would do 105 / 1.86, which gives you a timing value ~ 60t or so. Sometimes loosening tRFC up improves performance, as a more consistent queue of data from ram to cpu even though its slower to arrive still leave less unused clocks wasted rather than intermittent bursts then traffic jams and so on.,
other timings dont seem to have as large an influence as these do.
skews can have a large influence, and they are only relevant to a given frequency. they do change as you get farther from the previously skewed target frequency. you need to figure out how your particular board responds to skew changes and when it likes/dislikes them. it's a lot of trial and error, and guesswork. sometimes you can pick out which way skews need to be, but its not always obvious unless you are using really high dram frequency and fsb.
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