PLL is phase lock loop voltage, has nothing to do with CPU temps. If you have Loadline enabled the PLL will be higher than bios settings. Mine runs 0.05-0.1v higher than I set. Ie. I set 1.68V CPU PLL and real is 1.76V or so.
Good luck with PL 6. You need a lot of vNB for that, and on 333 Strap timings are generally too tight. Try slacking AI Clock Twister down to light if you want to run PL6. I have no problems with PL7. My ram won't stay stable at 1200mhz either. It's most likely the ram. I finally managed to post at 500FSB, 7x500, using 333 strap and 5:6 divider but I get display lockup after 5-6mins of mem testing. I need to go over all my secondary/tertiary mem timings and make sure they comply with JEDEC minimum windows. My rampage refuses to post with 1:1 divider at 333 or 400 strap and 500FSB.
Those results are about the right ball park. If you want latency tighter you'll need to do a lot of trial and error. One thing to note though, FSB_VTT is designed to limit overshoot for vCPU. If you raise vCPU above VTT then the CPU's pull in noise filter doesn't do its job anymore, It's also designed to prevent crosstalk and noise jitter between clock domains from what I understand.
FSB_VTT is semi important to keep aligned reasonably well with vCPU, it limits overshoot and controls max deviation of FSB_SWING voltage between rising and falling edges of the clock signal. GTL_REF[3:0] limits the undershoot of FSB_SWING, and these both keep the voltage within V(IL_H) and V(IH_H) limits. These are respectively, Host GTL Voltage in Low and Host GTL+ Voltage In High.
http://www.intel.com/Assets/PDF/datasheet/319122.pdf
If you want an idea on what exactly you break by fixing something else, take a read of this datasheet for the X48. Should help u understand a little more deeply on how to get around some problems and what causes them.
You can also find the Processor Sequence datasheet here for the Q6xxx 65nm series. It lists all the CPU voltages in regards to chipset.
http://www.intel.com/design/processo...hts/315592.htm
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