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  1. #1
    Registered User
    Join Date
    Nov 2006
    Posts
    29
    hi guys,
    i'm testing my new Q9650 "ES" on the Rampage Formula, i've found my stable setup at 467x9 with 1,36volts. are my settings "safe" for a daily use of a 45nm? i'm with CPU PLL @ 1.54 (bios value), FSBT @ 1.36 in bios = 1.26 in HW monitor and everest, CPU GTL @63x. Temp MAX 61-61-60-60 °C, in average it is 54-56°C.

    As i've read around here in XS and in other forums i'm into the safe values to keep the cpu safe, can you confirm?


    AI Overclock Tuner.............................. Manual
    CPU Ratio Setting............................... 9.0
    FSB Strap to North Bridge....................... 333MHz
    FSB Frequency................................... 467MHz
    PCI-E Frequency................................. 101MHz

    DRAM Frequency.................................. DDR2 - 1120MHz
    DRAM Command Rate............................... 2N
    DRAM CMD Skew on Channel A...................... AUTO
    DRAM CMD Skew on Channel B...................... AUTO
    DRAM CLK Skew on Channel A...................... Delay 300ps
    DRAM CLK Skew on Channel B...................... Advance 300ps
    DRAM Timing Control............................. Manual
    Primary Timings
    CAS# Latency................................ 5T
    RAS# to CAS# Delay.......................... 5T
    RAS# PRE Time............................... 5T
    RAS# ACT Time............................... 15T
    RAS# to RAS# Delay.......................... AUTO
    REF Cycle Time.............................. AUTO
    WRITE Recovery Time......................... 11T
    READ to PRE Time............................ 4T
    Secondary Timings
    READ to WRITE Delay (S/D)................... AUTO
    WRITE to READ Delay (S)..................... AUTO
    WRITE to READ Delay (D)..................... AUTO
    READ to READ Delay (S)...................... AUTO
    READ to READ Delay (D)...................... AUTO
    WRITE to WRITE Delay (S).................... AUTO
    WRITE to WRITE Delay (D).................... AUTO
    Tertiary Timings
    WRITE to PRE Delay.......................... AUTO
    READ to PRE Delay........................... AUTO
    PRE to PRE Delay............................ AUTO
    ALL PRE to ACT Delay........................ AUTO
    ALL PRE to REF Delay........................ AUTO

    DRAM Static Read Control........................ Disabled
    AI Clock Twister................................ Lighter
    AI Transaction Twister.......................... Manual

    Common Performance Level.................... 07
    Pull-In of CHA PH1.......................... Disabled
    Pull-In of CHA PH2.......................... Disabled
    Pull-In of CHA PH3.......................... Disabled
    Pull-In of CHA PH4.......................... Disabled
    Pull-In of CHB PH1.......................... Disabled
    Pull-In of CHB PH2.......................... Disabled
    Pull-In of CHB PH3.......................... Disabled
    Pull-In of CHB PH4.......................... Disabled

    CPU Voltage..................................... 1.375...V (1.36 in HW monitor)
    CPU PLL Voltage................................. 1.54V
    Northbridge Voltage............................. 1.55V (1.53 in HW monitor)
    DRAM Voltage.................................... 1.90V
    FSB Termination Voltage......................... 1.36V (1.26 in HW monitor)
    South Bridge Voltage............................ 1.1V (1.07 in HW monitor)
    SB 1.50V Voltage................................ 1.5V
    Loadline Calibration............................ Enabled
    CPU GTL Voltage REF............................. 0.63x
    NB GTL Voltage REF.............................. 0.67x
    DRAM Controller Voltage REF..................... DDR_REF
    DRAM Channel A Voltage REF...................... AUTO
    DRAM Channel B Voltage REF...................... AUTO

    CPU Spread Spectrum............................. Disabled
    PCI-E Spread Spectrum........................... Disabled
    Last edited by crash2k; 07-23-2008 at 10:52 PM.

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