AMD 45nm Deneb Pictures, CPU-Z and Super Pi Results

[mAJORD]

CPU-z is reporting NB speed as 1800Mhz on one of the SPi runs

[NightCrawler™]

Looks good so far... very pleased to see those clocks...!

[drfedja]

The L3 size improves the performance in Super Pi for sure, but I doubt that 12% are delivered from the L3 size alone. Since I can't open the page I wonder what is the NB & L3 frequency. I hope for more benches soon.

Maybe AMD engineers little tweaked K10 core with load ahead of store and they finally done right with OoO load execution.

It has 3 pipelines, just like Agena. As for the pipeline length I'm pretty sure it is same as on Agena, 12/18 ALU/FPU stages.

Acutally it has 2 pipelines. One integer, and one floating point with separate schedulers for integer/memory and floating point pipeline. These pipelines has 12 stages for integer and 17 stages for floating point.
K10 has 3 integer units, 3 AGU units and 3 FP units.
Core 2 has also 3 128-bit wide FPU ,3 ALU and 2 AGU units, but it can decode up to 4 instructions per clock, usually 3 arithmetic + one memory, because Intel PR machinery says that they have 4-way CPU, and other guys haven't. :d
I can't tell how much impact on performance has 4-way decoder on Core 2, but I am sure in that the main reason for good performance is good prefetch in combination with big L2 cache. Also, low latency L2, inclusive architecture, good branch predictor and high associativity L1 may bring few percent of performance.

What K10 needs is higher core, L3 and NB clocks, lower cache latencies, wider cache and some architectural improvements.

I agree with that, but it also needs better prefetch. When CPU needs data from memory IPC factor drops significantly. With better prefetch algorithms CPU can access data from L1, L2 or L3 without that significant performance drop. If CPU hasn't that smart algorithms IMC or better IMC can't help there.

[Nedjo]

time of production: somewhere between April 14. and 18.!!!

Wasn't Shintai that wrote somewhere that AMD wil not be out with 45nm CPUs before middle of 2009?

[NightCrawler™]

Maybe he meant for consumers.....?

[Sparky]

Interesting! Keeping my eye on this one...

[Shintai]

Maybe he meant for consumers.....?

But I said 2009!!1111

Yes, usually some 9months+ from this stage to release. Making a few 100 chips is one thing, making millions is another.

But the chip currently look as a better improvement than expected.

[freeloader]

I wonder if there's a few more tweaks they can get in? Or are we basically seeing production silicon here? Looks good. Let's just hope AMD can stay afloat long enough to release these.

[justapost]

Nice clocks and too high voltages for 45nm. Stepping 0 that is.

[Macadamia]

If C0 can clock to 3.4Ghz already... *gasp*

Well, Agena did improve about 400-600Mhz on "peak" OC, but we need SB750 to really know how far the 65nms will peak.

[BrowncoatGR]

These should be DVT samples at this point. The results look very good but i'd like to see some real benchmarks. I disagree that prefetch is a problem for AMD though.

[Calmatory]

Only if they can keep the power consumption down. Doesn't really help to have a C2Q killer when the chip needs 200W from the board.

[Trunks]

I hope they get rid of that silly phenom name.
because that name isn't doing them anything good

[Kayin]

power consumption should go down from the 45nm process.

I'm getting one of these, unless they announce Shanghai for desktops.

[Trunks]

power consumption should go down from the 45nm process.

Yes, but how much

[postumus]

results look pretty good so far, with any luck these will come out sooner rather than later and we get a semblance of competition in the cpu sector.

[Rammsteiner]

If C0 can clock to 3.4Ghz already... *gasp*

Well, Agena did improve about 400-600Mhz on "peak" OC, but we need SB750 to really know how far the 65nms will peak.

Pretty much this. We cant for sure call Agena bad clockers 'yet'. I mean, testing OC's of a CPU with a bad register in your RAM isnt a smart thing either in the end, guess that's a good enough comparison with the SB600 problem.

Anyway, this was the last thing I expected to see today, Deneb. I like it, although as stated before I hope the Vcore can go down just a little bit more when OC'd.

However, I see opportunities to get that Super PI score quite a bit better actually. I mean, they only ran it with DDR800 with 5-5-5 timings and 1.8Ghz NB. Both parts can be tweaked better, a lot actually.

About the competition against Nehalem, well, I dont think it would beat Nehalem either. But we also have to keep in mind that Nehalem LGA1366 is aimed at enthusiasts and doesnt come cheap. 'Mainstream Nehalem' (what's it named again) thingy comes quite a bit later, Q3'09 IIRC?... If AMD gets things sorted now and get Deneb running well I think we might see it competing against the mainstream Nehalem.

I mean, they've like 9 months to observe Deneb from launch and if needed launch a revision. Eventually again with a few price adjustments to keep it competitive, but better than they're standing now though.

But well, time will tell. I just hope this isnt like a cherry picked Deneb though but just one out of a bunch picked randomly. And this Deneb is actually clocked on SB600 too. Maybe it's one of these not so picky motherboards. I hope they retest it on a SB750

[informal]

New AMD WR has been made .
The dudes who brought us these pictures from itocp.com did it :
http://www.itocp.com/redirect.php?ti...tpost#lastpost

All it was needed is 3484Mhz on Deneb to break it.Cooling was AIR.

1M 00min19.969sec Ivanqu & Sunny
AMD Phenom 9850 3484.32 1.56 TeamXtreem 6400 536 2.5 4-4-4-8
L
Air

New 45nm Phenoms are still not recognized properly so they show up as 9850.
The score is exactly 12.5% better clock/clock than tweaked Agena core (MILANS did the next best K10 result,took him 3621Mhz,with tweaked L3@2.1Ghz and low latency ddr2 to get 21.625s score).

[Start]

I wonder how many pipelines it has. If there were able to shorten them and keep the same or higher clockage then

Usually when you have fewer pipeline stages, you tend to clock the CPU clock much slower to get performance similar to an architecture with more pipeline stages and a faster clock.

[GoThr3k]

power consumption should go down from the 45nm process.

i dont think power consumption well go down by a lot without using high-k

[Calmatory]

It needs high-k indeed. Wasn't AMD doing something like that with IBM? If it was, wasn't it for 32nm though? Or are they implementing it to 45nm?

[GoThr3k]

It needs high-k indeed. Wasn't AMD doing something like that with IBM? If it was, wasn't it for 32nm though? Or are they implementing it to 45nm?

i thought they were implementing it in a second generation of 45nm, forgot the codename, but if you search you will find plenty of info i think

[justapost]

Hmm at 2.8GHz the chip still requires only 1.225V that looks abit better than 3.44GHz at 1.57V

[ryboto]

These should be DVT samples at this point. The results look very good but i'd like to see some real benchmarks. I disagree that prefetch is a problem for AMD though.

I thought I read about DVT samples being available a few months ago?

[GoThr3k]

These should be DVT samples at this point. The results look very good but i'd like to see some real benchmarks. I disagree that prefetch is a problem for AMD though.

someone willing to explain the differences between the prefetchers of AMD and Intel?