Originally Posted by Helmore
With GDDR5 the distance to memory does not have to be equal on all chips anymore, that's because the chips do a little training on start up to see what the best way to work is and this way they can adapt to different circumstances. It's also useful for overclocking by the way, they chips will set latencies and other values on boot up and stuff like that and this will increase the overclocking capability these chips have by design. One more thing about GDDR5, the lead designer of GDDR5 is on AMD's employee list.
As for utilizing half the memory bus for communication, well I don't think that's a very elegant approach as you are trying to make 1 chip for both midrange and the enthusiast market and you will need the bandwidth in the enthusiast market. Then one more thing, I think you can come up with a higher data rate per pin connection if you make a more 'proprietary' connection and besides, I don't think you need a connection that is at the full speed of the memory system for each chip, you won't be using that connection for doing AA resolve and AF and stuff like that. It's only meant to share data that needs to be shared, like state changes, textures and stuff like that and you probably only need 1/3 to 1/2 of the full (per chip) memory bandwidth to do that.
Ahh but you wouldn't be.. it's not set in stone how much is used for what... The communication happens on the internal bus, this is shared for inter die, and memory traffic. So as inter core comms vary, I guess one down side is that it would reduce the memory bandwidth available slightly.. However the bus to memory modules(external) doesn't have to be this full size. I am simply envisioning a way to build dies from the ground up for mcm. Low end, would have one die, thus half memory bw, higher end has 2 or 4, thus double or quadruple.. Depending upon what is required. The idea is to have the memory controllers for ea batch of chips ( x per die) as peers on a larger bus along with compute/setup parts of die. In this fashion, memory bandwidth and inter die comms is on one standard bus. which if designed properly could be expanded x^2. (of course some finite limit.. but lets think in terms of 1 to 4 dies) Or, it could be done with something more akin to HT links, as in 2 or 3 per die, and then in reality adjusting for latency, you'd have ability for mcm for cheap midrange (4850 - 4870) Dual mcm (4870 x2) and single die for low range (46xx) Additionally think of dropping one of these onto a chipset package...
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