Nehalem is designed electrically for 45nm Metal, penryn wasnt.Originally Posted by bowman
Nehalem is designed electrically for 45nm Metal, penryn wasnt.
Crunching for Comrades and the Common good of the People.
how was penryn not designed for the high-k dielectric?
Based on tick-tock,
the process comes first and then a new architecture that is built on that process.
Penryn is just a die shrink of Conroe with a few enhancements. It was originally designed for 65nm. Nehalem is designed from the ground-up to be built on the 45nm process technology.
Even if they've enhanced it there's supposed to be gains from designing it ground up for the already tried and true process technology.
Exactly... and there are numerous reports that when Intel caught wind of AMD doing a native quad on 65nm, they simply admitted they couldn't do it. An interesting statement given the struggles that AMD has had but at the same time a bit of endorsement to AMD's engineering to have been able to pull it off.
At any rate, I think both AMD and Intel will demonstrate that 45nm is "the" process at which a native quad becomes really viable.
It wasn't when they caught wind of it, it was several months after AMD unveiled the barcelona design. And Intel's statement was more along the lines that it would be foolish to attempt it rather than they couldn't do it.
Considering the trouble AMD had getting this product to market, Intel was more or less correct it would appear. The whole advantage of Intel's MCM approach is simplicity, yield (costs), and time to market -- all of which has proven to be quite effective so far.
http://www.eetimes.com/news/latest/s...leID=201804316"At 65nm the die would be too big to hold four [Intel] cores and it would be so expensive it would not make sense," said Bryant. "Our 45nm process technology will allow us to do a monolithic quad-core design," she added.
Last edited by JumpingJack; 06-24-2008 at 06:16 PM.
One hundred years from now It won't matter
What kind of car I drove What kind of house I lived in
How much money I had in the bank Nor what my cloths looked like.... But The world may be a little better Because, I was important In the life of a child.
-- from "Within My Power" by Forest Witcraft
Yeah i remember the article with Pat Gelslinger (sp) saying that it was economical to do it for Intel. Maybe 45nm yields are good enough to actually make a monolithic quad core.
It would seem that based on the limited time we've seen tick-tock in motion that the ticks's get the monolithic dies and the tocks don't.
Presler was a tick, and dual die dual core.
Conroe was tock and it was monolithic dual core.
Penryn was tick and dual die quad core.
Nehalem is tock and is monolithic quad core.
Because the ticks don't matter as much as the tocks. The ticks are just used to get the manufacturing process mature enough for the tocks.
Although how they're going to do the 8 core Nehalem on the 45nm process and make it affordable is beyond me.
yeah so although it's a die shrink of Merom, it was designed for High-K. The whole point of doing that was so that by the time Nehalem rolled around, the 45nm High-K process was mature enough to make a larger die without taking too big a hit on yields. I don't see how because of that Penryn wasn't designed for High-K dielectrics.
I also heard that the lithography doesn't actually get the transistor to 45nm and that they have to do some etching to get it down to the 45nm mark.
You've got it backwards. Penryn is a derivative of the Merom family. Merom was designed specifically for 65nm and Penryn is a "die shrink" with minor updates for the 45nm node. Nehalem is designed specifically for 45nm and Westmere is the derivative process shrink of Nehalem on 32nm. Similarly, Sandy Bridge is specifically designed for 32nm and so on and so forth.
Penryn is a shrink of Merom/Conroe, while I suspect there is opportunity to design to the 45 nm strengths, the basic circuit design, transistor expectations, etc. were fundamentally rooted in the 65 nm process technology. Same concept about K8 and 65 nm Brisbane, K8 was initially founded in the 130 nm node.
The most fascinating thing about Intel's 45 nm technology is the performance of the PMOS, and if you read up in the literature (basic design stuff, the IBM Journal site has some good info there), the ratio of PMOS to NMOS performance affects the overall approach.
For example ... IBM maps out beta, the ratio of PMOS to NMOS as they designed their circuits for the Power 6 (a ground up design)
http://www.research.ibm.com/journal/rd/516/curran.pdf
As such, deisgners fashion the geometry and layout of their transistors with this information in mind. Since Nehalem has gone modular and totally reworked, it is expected the designers will leverage the PMOS performance to the fullest advantage.
This is what Gelsinger meant when he said
I am not sure how Intel will ultimately use this, based on die size, transistor count, etc. Anandtech showed a 10% increase in performance for a much larger total die than current Yorkfield. I suspect they are leveraging it to keep thermals low at the same clock... not sure."The Core micro architecture is built for 45nm and 65nm. In the case of Nehelam, it is natively architected to take full advantage of 45nm,"
"In that sense it is really going unlock the full potential of that process technology's capabilities beyond what the Penryn was capable of doing."
Last edited by JumpingJack; 06-24-2008 at 06:36 PM.
One hundred years from now It won't matter
What kind of car I drove What kind of house I lived in
How much money I had in the bank Nor what my cloths looked like.... But The world may be a little better Because, I was important In the life of a child.
-- from "Within My Power" by Forest Witcraft
i think i see what you're talking about.
What you're saying is that Intel changed the transistor ratios for Nehalem as opposed to just changing lambda (design rules)?
But wouldn't they have to have changed the L and W for Penryn anyway? For a simple PMOS process, the length of the transistor is determined by first level lithography and the width, second.
So since they nave a 45nm pitch, they would have had to change the L and W anyway. Had they taken Conroe and brought it directly to 45nm, then yeah, you can just change Lambda, but that's not the case.
I guess what i'm wondering is what you wanted me to read on the PDF.
I'm asking all these questions because i'm doing a VLSI lab right now.
More or less... I have made a hobby out of reading and tracking the device physics as the industry as progressed. PMOS is typically a 'slower' transistor (all things being equal) than an NMOS transistor. This is because the majority charge carriers for a PMOS device are holes where as NMOS they are electrons. The effective mass of holes often out weight that of electrons, so the hole mobility tends to be lower (hence slower transistors).
In short, take what you can get... if your PMOS is weak, then you rework your circuits to use as few PMOS as possible or you account for the difference in the design of the bitcell and transistor geometry (notice the gate length between PMOS and NMOS are different in the IBM paper I referenced above, PMOS being shorter to account for the fact that PMOS is slower)....
It isn't that Intel turned to the beta as a major component, it is that they developed a good PMOS transitor which the Nehalem designers can augment around and take advantage of....
Jack
One hundred years from now It won't matter
What kind of car I drove What kind of house I lived in
How much money I had in the bank Nor what my cloths looked like.... But The world may be a little better Because, I was important In the life of a child.
-- from "Within My Power" by Forest Witcraft
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