ddr2 low tras trick???4-4-4-4 ?

[railmeat]

hi all,

ok i seen ALOT of guys running ddr2 with timings such as 4-4-4-4 etc with the tras matching the other 3 alpha timings and i had no real stabilty luck with that setup and most of the time will not boot up period.

so basically my question is the voltage to vdimm or nb setting set alot higher to have tras so low and pass stabily?
or is it the deeper subtimings that must be tweaked in accordance to run a matching tras number?

i seen eva-2000,loco and many others with these amazing ddr2 tras numbers and would really like to know any good basic tips as a TRUE baseline.just something i can work around and get my tras as low as my first 3numbers(eg 4-4-4-4).tras seems to be the hardest hitting stabilty timing of the group to run a solid machine vs a flacky one.i have 3 VERY good sets of ram to start off with surrounded by VERY good hardware.thanks in advance.



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my 3 sets of ram i use

1.
my best set-2 Gb Kit (2x1Gb) Cell Shock 5-5-5-15 1000Mhz (Memory Chips: Micron D9GKX)
voltage never above 2.2 and 2x40mm fans on em always
http://www.tankguys.com/product_info...oducts_id=1714

2.
OCZ SLI-Ready Edition 2GB (2 x 1GB) 240-Pin DDR2 SDRAM DDR2 1066 (PC2 8500)---(Memory Chips: Micron D9GMH)
http://www.newegg.com/Product/Produc...82E16820227181

3.
Supertalent---2x1 gig ddr800 (Memory Chips: Micron D9GMH?????????) there new in box on shelf,never opened yet.
http://www.newegg.com/Product/Produc...82E16820609027

[DonBanana]

You mean something like this?



There is no secret behind, just good ICs.

Edit: Kingston Hyper X D9GKX 2GB 2.2VDimm

[zsamz_]

best for cas 4 is d9gkx 4-4-4-12 1100mhz 2.24-2.32v
you gotta test ur ram n try lol

[Tony]

Low tRAS is only good for pi, anything else and the pages are closed to fast and the controller may be forced to re read.

Low timings are not always best.

[railmeat]

Low tRAS is only good for pi, anything else and the pages are closed to fast and the controller may be forced to re read.

Low timings are not always best.

well said tony and agree with the pi note.ty sir and all of u.....

[Quintero]

Low tRAS is only good for pi, anything else and the pages are closed to fast and the controller may be forced to re read.

Which platforms are you referring to?

[George_o/c]

Which platforms are you referring to?

He is talking in general ... If you like 2D benching lower your tRAS it will help a lot ... But running an everyday system at 4-4-4-12 2T is better than 4-4-4-4 2T ... You won't see any difference, instead you 'll only make things worse ...

[George_o/c]

Which platforms are you referring to?

He is talking in general ... If you like 2D benching lower your tRAS it will help a lot ... But running an everyday system at 4-4-4-12 2T is better than 4-4-4-4 2T ... You won't see any difference, instead you 'll only make things worse ... For example I run 24/7 with my DDR @ 3-3-3-8 ... If I lower the tRAS to 5 (3-3-3-5) I get a boost in SPi, PiFast (WPrime does not get better, as it is mostly about CPU power and not memory timings ), 3D Mark 01 Lobbies I've also tried though, 3-3-3-5 for 24/7 and the system is considerably slower ...

[-n7-]

I could do 4-4-4-4 with my Team Xtreem D9GMH.

And yeah, it was slightly better for SuperPi; worse for pretty much everything else.

[Quintero]

He is talking in general ... If you like 2D benching lower your tRAS it will help a lot ... But running an everyday system at 4-4-4-12 2T is better than 4-4-4-4 2T ... You won't see any difference, instead you 'll only make things worse ...

4-4-4-4 can never be real, and it would be hard to predict what value it'd make different controllers default to. That's one reason why I agree that tRAS 4 could cause unwanted results.

But I also know for a fact that at least some controllers (K8 / K10) do not forcibly close pages when tRAS elapses, and to implement such behavior would be plain unnecessary. While I am less familiar with other systems, it is very hard for me to see why designers would make that decision. Current designs employ a range of methods to control load ordering, most of which would've been meaningless if they didn't "outrank" tRAS.

Idle Cycle Limit determines when to close pages (high tRAS might unnecessarily delay row switching).
Dynamic Idle Cycle Counter modifies the user-selected ICL based on page traffic history.
Bypass Max regulates the number of bursts that are read in succession before switching row, bank and/or rank (which may or may not force rows to be closed).
R/W Queue Bypass features allow the controller to postpone a turnaround from read to write.
Design, configuration, data pattern and interleaving techniques also factor into the memory's behavior.

High tRAS may well reduce the versatility and success rate of the above-mentioned features, so the story just does not add up for me.

[eva2000]

depends on memory modules themselves and board memory controller

My old ocz pc2-8000 titantium vx2, gskill 6400 hz d9gmh all can do 4-4-4-4, but my early sets of crucial ballistix pc2-8500 tracer/non-tracer don't like lower than 4-4-4-8 without too much vdimm and team 6400c3 d9gmh only manage 4-4-4-5. My last few sets of crucial ballistix non-tracer double sided handle 4-4-4-5 fine.