Intel Yorkfield/Wolfdale new steppings

[pmp]

Hi,

New steppings are now available.
Yorkfield C1 went for E0 stepping, Wolfdale M0 went for R0.

E0 introduces new power states (C2E, C3, C4 called as Extended Stop Grant State, Deep Sleep State, Deeper Sleep State), changes in PECI implementation, new two instructions added, halide free package and some other minor changes as well.

OC abilities atm unknown

J.

[G.Foyle]

*Hopes for higher FSB with Yorkfields*

[AAbenson]

i think its a bit too early to expexct a G0 like revision for the 45nm technology just yet

[OBR]

*Hopes for higher FSB with Yorkfields*

if you know how to make it with GTL it is easy ... my Q930 works rock stable at 500MHz FSB ...

[webwilli]

Fudzilla say R0 for Yorkfield:

http://www.fudzilla.com/index.php?op...7509&Itemid=35

[Kabauterman]

dont understand why intel changes the steppings,

M0 isn't realy available on market and C1 is also very new

[[XC] gomeler]

o rly? Wonder when we'll see some results with these.

[Blasar]

*Hopes for higher FSB with Yorkfields*

Same here.

But i think that the origin of the FSB problems is not, only, the CPU, and maybe a CPU + Chipset + Noob skills@OC (me included) mix.

[dinos22]

what's happening to C0 wolfdale (E8xxx series)
M0 Wolfdales are E7xxx series chips

M0 i have here (E7300) does not like 965 chipset at all.... 480MHz MAX FSB

but my Gigabyte X38 board goes to 520Mhz FSB while Asus X38 is strangely limited to 480 as well

[Jacky]

dont understand why intel changes the steppings,
M0 isn't realy available on market and C1 is also very new

just a guess: optimising yields or other variables that are important to them.
and afaik they are not available merely because Intel is fab-capacity constrained at 45nm and serving high-asp markets first (server, laptop).

Though, I don't even know what such an early revision is good for? Anyone enlighten us?

[nullface]

Bah, just bought a E3110 C0, i hope these clock worse then

[pmp]

Bah, just bought a E3110 C0, i hope these clock worse then

Choose is always yours - quit XS, use your PC, take your time well!
Or bother your mind if C0 is worse than E0

Seriously, i'm getting mentally older latelty :-)

[Richard Dower]

I just emailed Tankguys asking if they will stock them as they seem to be rather good at stating what stepping CPus they have and they also guarantee a stepping.

[TankGuys]

I just emailed Tankguys asking if they will stock them as they seem to be rather good at stating what stepping CPus they have and they also guarantee a stepping.

We're working on it

[Richard Dower]

We're working on it

Hehe!

[Warboy]

Epic win....Too bad i just RMA'd my Q9450 not less then a few days ago and got a older C1 stepping....

[MarlboroMan]

already posted it a week ago, but not here on the news... its HERE

so, again, the real info on Intel's documentation:



some news to future E8400/E8500 or E3110 owners
New stepping E-0 C2D are already sampling, and will be out sometime LATE August.

Description of Change to the Customer:
The Intel® Core™2 Duo Processor E8500, E8400 and Dual-Core Intel® Xeon® Processor E3110 will
undergo the following changes for the C-0 to E-0 stepping conversion:
• New SSpec and MM numbers for the converting products
• CPUID will change from 0x10676 to 0x1067A
• Power Status Indicator (PSI) is supported
• PECI implementation change
• New instructions added – XSAVE/XRSTOR
o New ISA extension for save/restoring context of x87, SSE, and future processor state
• New feature added - ACNT2
o Improved mechanism for determining processor utilization. To be used for more efficient
P-state determination.
• Package change to Halide free package


Customer Impact of Change and Recommended Action:
• No BIOS or board changes required for ACNT2 feature. The operating system (if it supports this
feature) will check the feature flag and enable this feature.
• No Bios changes required for XSAVE/XRSTOR. Refer to Intel® 64 and IA-32 Architectures
Software Developer’s Manual Volume 3A: System Programming Guide and Intel® Advanced
Vector Extensions Programming Reference for details.
• Power state Indicator (PSI) will require new circuits on the board to support the feature. Please
refer to the Platform Design guide document for chipset that support the PSI feature.

[Richard Dower]

Interesting Marlboro...thanks, explains alot more....i guess we might see a PCB revision then to support that PSI feature. Perhaps Asus and GB will be the first to implement the changes in PCB design. So is there no news on the Quad core stepping change?

[MarlboroMan]

For the quads, only Xeons series X/E/L5xxx that I know for now.
The xeons quads E-0 stepping consume less power (has lower TDP) than the C-0 ones. I don't know by now if this applies to desktops C2Q.

[STEvil]

Just had a new X3350 shipped direct from Intel (technically it made a stop in Vancouver first), maybe i'll get lucky! :o

[systemviper]

Tank Guys #1

[MarlboroMan]

Just had a new X3350 shipped direct from Intel (technically it made a stop in Vancouver first), maybe i'll get lucky! :o

if it isn't an ES chip = its not an E-0

[STEvil]

Darn :/

[dinos22]

thanks for the update MarlboroMan

so E0 is next
i wonder if they will still like 965 chipset for high FSB or even better some of the newer ones hehehe

[Monkeywoman]

New two instructions added

does this mean that these are slightly faster?