Ok, dropped in the Q9450, reset cmos, rebooted, jumped into voltages and saw that GTLref voltage for the 2nd core was at +45mv (it was set to auto). I manually set all of them to 00mv.
Why did this happen? Is it supposed to be that way?
Ok, dropped in the Q9450, reset cmos, rebooted, jumped into voltages and saw that GTLref voltage for the 2nd core was at +45mv (it was set to auto). I manually set all of them to 00mv.
Why did this happen? Is it supposed to be that way?
I don't know how the board determines the auto voltages, but playing around with the GTL settings can improve your maximum overclock especially on a quadcore chip. Takes a lot of trial and error to find the optimum settings however and every chip is different. With my q9450 on 790i so far I've had best results setting all four lanes to +30 millivolts.
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Finally a response!!! Thank you...!
Im still wondering why it only set 1 of them to +45mv.
I googled a little but couldnt get any other info. Does setting these up higher raise the core voltage also?
Its a reference voltage for signaling so (in my limited understanding) it is not additive to vcore. There's a detailed explanation of it at the techrepository here: http://www.thetechrepository.com/showthread.php?t=87
Raja's overclocking guide for the DFI P35 at Anandtech (sorry, too lazy to look up a link) also has a lot of good discussion about the GTL settings. Unfortunately I don't know how the DFI settings guidelines apply to the 790i bios which is different.
Basically all I did on the 790 was find max fsb with GTL on auto, then start adding 10 mv at a time. I was eventually able to squeeze another 10-20 stable fsb out of a q9450 doing this. Its a very touchy setting -- the difference between being OCCT stable and not posting can be as small as 5-10 mv.
Good luck!
EDIT: Here's some great specific info on calculating GTL settings for the 790i: http://www.anandtech.com/mb/showdoc.aspx?i=3283&p=18
Last edited by Aivas47a; 04-11-2008 at 12:47 PM.
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How to adjust your gtlref lanes.
I have an EVGA 780i and I found this approach to work well for me.
1) Adjust your vtt to a low enough voltage so that prime 95 will fail after one or two iterations. ( I had mine around 1.5 volts @4.2 GHz.)
2) A good starting point for me was .30 on all four lanes.
3) boot up and start prime 95 on all for cores. and see which cores fail first.
4) Gradually raise or lower the voltage for the particular core that is failing first. (this can be a time consuming thing because it really is trial and error.) I found that core 2 would fail first and than core 1. core 0 and 3 were pretty stable until I got too high on the gtlref voltages. The funny thing was that it seemed core 1 needed more voltage than the rest and core 2 needed less. After some time I got all 4 cores to go about 3 iterations before failing. ( I ended up at .40, .50, .25, .40.)
5) now go in and raise your vtt up around .25 volts higher. (1.525 in my case) my system is now much!!! more stable than it was when I had them all on auto.
I hope this is helpful for someone because I know I was at a loss with a system that was un-stable for some time until I figured this out. GOOD LUCK!
I like the theory there is just one issue with it...each adjustment is NOT for each core, its for each die.
SOURCEThis can get tricky though as each die receives two GTL reference voltages - one for the FSB Data Bus (running at the full FSB transfer rate) and one for the FSB Address Bus (running at half the FSB transfer rate). This means CPU GTL_REF0 Ratio is for the Core 0/1 Data Bus, CPU GTL_REF1 Ratio is for the Core 2/3 Data Bus, CPU GTL_REF2 Ratio is for the Core 0/1 Address Bus, and CPU GTL_REF3 Ratio is for the Core2/3 Address Bus. CPU GTL_REF2 Ratio and CPU GTL_REF3 Ratio will have no affect with a dual-core CPU installed, in which case CPU GTL_REF0 Ratio is for the Core 0/1 Data Bus and CPU GTL_REF1 Ratio is for the Core 0/1 Address Bus. As a rule, adjustments are normally made to FSB Data Bus values first. These lines are consistently heavily loaded and as such are more susceptible to the detrimental effects of reduced signaling margins.
Also, how do you get your voltages, 1.5v for example? Do you take your CPUv and add the GTLREF # to it?
That was written using datasheet information for 771 pin processors. Intel used separate data and address GTLREF voltages on those processors. It appear from the limited amount of information available that starting with 775 pin (P4) processors a single GTLREF voltage was used for the data and address bus.Originally Posted by jas420221
The 775 pin processor configuration goes like this. 1 core, 1 GTLREF voltage. 2 cores, 2 GTLREF voltages. 4 cores, 4 GTLREF voltages.
Cant believe everything you read I guess... thanks for the clarification! Though if I may, do you have any links of which you speak?
In the beginning we all assumed that was the proper configuration. When the ICFX3200 came out GTLREF tuning was something new. To see how the configuration changed one needs to read the relevant processor datasheets from Intel.
The 1.5 volt is the CPUv and the gtlref voltages are separate.
Also I did notice that adjusting one core did have a slight effect on another. ex. upping the voltage to core one, while adding stability to that core, may decrease stability in another. That is why it takes a while to find just the correct combination.
So what do you think the MAX GTLref volts are?
Max GTL ref voltage will be your FSB VTT voltage. GTL ref is a divider of the VTT voltage, think of it like a percentage. As such 100% would make GTL ref = FSB VTT.
Thank you...though it doesnt measure in percentage, it measures in mv. Its 67% of vtt, + whatever settings you add to it....right?
Usually around 67%, Intel has changed it with different CPUs. That may be why the BIOS defaulted to +45mV.
Here's the best way to setup GTL ref levels. Get to your desired OC frequency, or what ever you feel is the max stable point.
Then one at a time, move the GTL ref up until you find the max point that is "stable". Then move them down, one at a time until you find the min point that is "stable". You can do max then min for a single one then move to the next. The order doesn't matter. Now calculate the center between the max and min for that specific GTL ref. Then set each one to its center point.
To test if it's stable, you can use any form of test you want. Just make sure it's consitant and repeatable. Booting to windows is a good test to use, because it's quick, consitant and repeatable. Sure, if it "passes" boot to windows then you run Prime95 it might fail. But that doesn't matter, as long as you use the same test to find the min and max point. Your not looking for absolute min and max stability points. Just a relative min and max so you can calculate the center point.
This will ensure you have the most margin, or headroom, above and below your set point. It will change if you change voltages or frequency, so if you do this margining procedure at default then increase the FSB clock by 150MHz it will be way off.
Last edited by Anubi; 05-04-2008 at 10:04 AM.
The only problem with this method is the upper end is unknown. The high side GTLREF can be driven hard into overshoot and still produce a valid signal as long as the resultant ringing can be clamped fast enough. So what appears as the upper bound has actually been exceeded by a wide margin. And as a side note, constant overshoot of a high enough magnitude will damage the circuit it is being input to.
Praz,
Not sure I follow, GTLREF is a DC reference voltage, it's not switching. It can't go higher than the FSB signaling voltage if the circuit was designed correctly. So there isn't any risk of damage from adjusting the reference voltage.
I'm not talking about changing the signaling voltage (FSB VTT) just the GTL reference voltage.
Switching signal overshoot and undershoot. The closer GTLREF is moved towards VTT the more likely overshoot will occur.
An excellent artical detailing FSB signaling and the interaction with GTLREF. http://www.thetechrepository.com/showthread.php?t=87
As is shown in the image you attached, GTLREF is a flat DC signal.
The actual FSB signals are switching and do have overshoot and ringback. Ringback and overshoot occur regardless of GTLREF voltage level, it doesn't matter where you put GTLREF it won't change the signaling waveform, and will have no affect at all on the ringback and overshoot. What GTLREF voltage level changes is how the receiver interprets the logic level as either high or low.
Looking at the image, you can see if you raise GTLREF voltage you'll reach a point where it will hit the low ring back on the FSB signal when it's signaling a logic high. When that happens you get a failure. And if you lower the GTLREF voltage you'll eventually hit the high ring back on the FSB signal when it's signaling a logic low. Again, you'll get a failure.
You don't want either of these failing cases to happen on your system so the best place to locate the GLTREF signal is in the middle between these two failing points. That way you have the most margin between them. The only way to find these failing points, and thus the middle as far away as possible from them, is to physically move the GTLREF voltage up and down to locate them.
Last edited by Anubi; 05-04-2008 at 06:44 PM.
In a properly designed and tuned circuit you will not have overshoot. I feel another article worth reading is Understanding GTL Reference Voltage.
Last edited by Praz; 05-05-2008 at 03:43 AM.
Both are good articals. Overshoot and ringback are unavoidable when trying to balance edge rates and frequency.
The important take way from this is that VTT voltage is used for FSB signalling, and Vref is a DC voltage derived from VTT which is used by the agents on FSB to determine logic high or low values.
Adjusting Vref to it's optimal level can improve your voltage margin, and thus, better overclocking.
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