AMD Says That K10 Problems Will Only Be Cured by K11

[savantu]

Thanks for replying.



Could you elaborate on what problems?

I'm just a hobbiest with a interest in the technology and my limited knowledge is gleaned mainly from picking out those who know what their actually talking about in various forums and firing off the odd question. From that what I gather is immersion lithography is essential by the 32nm node so in utilizing it with the current node AMD/IBM is if anything benefiting for the additional experience gained.

True.Using 45nm immersion means they gather experience for the 32nm transition.

Intel OTOH used dry at 45nm allowing maximum capital reuse from 65nm.The downside was they needed double patterning which cut FAB output ( see shortages of Penryns ; this will be solved as more FABs come online - Intel plans 4 45nm FABs ).

But it won't be easy either for AMD/IBM at 32nm.Why ? Because they will change from low-k SOI to high-k/metal bulk SOI.
I'd say it is more difficult to change the process than the tools ( since there are a few tool makers , Nikon , Canon , ASML ).Basically , the tools are the same for all , what matters is the process.

While it can produce lower yeilds relative to dry lithography again, from what I've read, AMD are actually doing very well in this regard. In contrast there have been yield issues suggested at Intel's reliance of dry double patterning. I know in Australia at least availablity for Penryns have until very recently been light on the ground and generally above list price.

Intel shipped 10 million 45nm CPUs in less than 6 months.While not many , they expect to crossover 65nm by Q3.If accomplished the ramp will be excellent , in line with former transitions.

[BrowncoatGR]

True.Using 45nm immersion means they gather experience for the 32nm transition.

Intel OTOH used dry at 45nm allowing maximum capital reuse from 65nm.The downside was they needed double patterning which cut FAB output ( see shortages of Penryns ; this will be solved as more FABs come online - Intel plans 4 45nm FABs ).

But it won't be easy either for AMD/IBM at 32nm.Why ? Because they will change from low-k SOI to high-k/metal bulk SOI.
I'd say it is more difficult to change the process than the tools ( since there are a few tool makers , Nikon , Canon , ASML ).Basically , the tools are the same for all , what matters is the process.


Intel shipped 10 million 45nm CPUs in less than 6 months.While not many , they expect to crossover 65nm by Q3.If accomplished the ramp will be excellent , in line with former transitions.

I think the low-k dielectric and high-k dielectric materials you are referring to are applied to different parts of the die. Maybe some of the more knowledgeable members in process technology can clear this up.

[azza21]

Does AMD ever get any good publicity these days, poor buggers
Please AMD get something right. All these bugs issue's, delayed products, false promisis regarding benchmarks etc...when will it end. I'd really love to see AMD get it right, hopefully this will happen when the 45nm chips see the light of day. They deserve a bit of good karma now

[Calmatory]

Does AMD ever get any good publicity these days, poor buggers
Please AMD get something right. All these bugs issue's, delayed products, false promisis regarding benchmarks etc...when will it end. I'd really love to see AMD get it right, hopefully this will happen when the 45nm chips see the light of day. They deserve a bit of good karma now

The fact is that AMD just SUCKS when compared to Intel. Intel is a GIANT. AMD is a just a small piece of dirt. How is a 160cm/45kg nerd supposed to beat a 140kg and 220 cm tall monster with bare hands? With luck, maybe. Thats what brought K7/K8 to their prime. Intel messed up with their products while AMD made good work.

Now even if AMD did god work, Intel would still dominate. Why? Because they are bigger. Better. Have more capacity, more engineers, they don't have to take risks etc. They can just kick AMD's ass because AMD is small compared to Intel.

Sad but true. Shanghai or Bulldozer won't really change the fact. ...unless Intel messes up with Nehalem, big time.

AMD isn't bad, Intel is just superior.

[gallag]

The fact is that AMD just SUCKS when compared to Intel. Intel is a GIANT. AMD is a just a small piece of dirt. How is a 160cm/45kg nerd supposed to beat a 140kg and 220 cm tall monster with bare hands? With luck, maybe. Thats what brought K7/K8 to their prime. Intel messed up with their products while AMD made good work.

Now even if AMD did god work, Intel would still dominate. Why? Because they are bigger. Better. Have more capacity, more engineers, they don't have to take risks etc. They can just kick AMD's ass because AMD is small compared to Intel.

Sad but true. Shanghai or Bulldozer won't really change the fact. ...unless Intel messes up with Nehalem, big time.

AMD isn't bad, Intel is just superior.

heres to hopeing for another k8

[flutie98]

I think the low-k dielectric and high-k dielectric materials you are referring to are applied to different parts of the die. Maybe some of the more knowledgeable members in process technology can clear this up.

The low-K dielectric is used during the metal interconnects as insulation to limit parasitic capacitance between current carrying lines. While the high-k is referring to the material used as the gate dielectric to boost the electric field strength and reduce the needed turn on voltage for the FET

[JumpingJack]

The low-K dielectric is used during the metal interconnects as insulation to limit parasitic capacitance between current carrying lines. While the high-k is referring to the material used as the gate dielectric to boost the electric field strength and reduce the needed turn on voltage for the FET

Absolutely correct .... high-k is needed so that the gate oxide can be made thicker at the eqivalent SiO2 capacitance and propogate electric field density into the channel in order to mitigate short channel effects and improve switching speed. The thicker the gate the farther the gate electrode is away from the channel and the direct tunneling leakage is much lower (falls off exponentially).

Low-k is desirable in the dielectric material that supports/separates metal lines that wire up the transistor. Wire delay or sometime called RC delay, is directly proportional to resistance (of the metal lines) and the capacitance generated between adjacent metal lines or frequency max indirectly proportional, however you want to look at it (delay~R*C). To lower the delay choose lower resistance wires (hence the move to copper some years ago, lower resistivity) or lower the capacitance, hence the push to lower dielectric constant (k) for the inter-wire support materials.

Jack

[Orthogonal]

Intel OTOH used dry at 45nm allowing maximum capital reuse from 65nm.The downside was they needed double patterning which cut FAB output ( see shortages of Penryns ; this will be solved as more FABs come online - Intel plans 4 45nm FABs ).

But it won't be easy either for AMD/IBM at 32nm.Why ? Because they will change from low-k SOI to high-k/metal bulk SOI.
I'd say it is more difficult to change the process than the tools ( since there are a few tool makers , Nikon , Canon , ASML ).Basically , the tools are the same for all , what matters is the process.

That's not entirely correct, the double patterning for Intel's 45nm will certainly take the extra time of 1 more pass, but that is not a limiting factor for why there's shortages of Penryn. The double pass is used on only 1 layer. All other layers are standard 193nm dry patterns, even 248nm for many metal layers. You're correct that they are capacity limited right now as fabs come online, but it has nothing to do with double patterning. In fact, double patterning is just as fast (or slow) as immersion litho, and quite a bit cheaper, so everyone will be subject to these timing constraints when they migrate to it.

Next, Low-K Interlayer Dialectrics and Hi-K/Metal Gate have really nothing to do with each other. In fact, BOTH will be (are) implemented in Intel's 45nm and IBM's/AMD's 32nm process. Intel definately uses Low-K dialectrics for the metal layers, it's just not trumpeted as much as the other camp. The reason you use low-k ILD's is to either mitigate cross-talk between metal interconnects or to be able to reduce interconnect feature size with the same relative cross-talk (or some combo of both). Considering that AMD actually has MORE metal layers than Intel I am curious as to how good their Low-K solution is.

High-K/Metal gate is a method to physically increase the thickness of the Transistor gate dialectric, while electrically making it thinner. Semi companies have reached the physical limit of gate oxide scaling for SiO2 (about 1nm) and will not be able to decrease it any further without significant gate leakage problems. A high-K dialetric now allows the industry to further scale down the gate stack dimensions for performance and reducing the effects of leakage and tunneling.

It is also unclear if IBM/AMD will use SOI or Bulk silicon processing when they transition to High-K/Metal gate although they will likely forgo SOI and move to Bulk since it should be "easier" and cheaper.

[savantu]

That's not entirely correct, the double patterning for Intel's 45nm will certainly take the extra time of 1 more pass, but that is not a limiting factor for why there's shortages of Penryn. The double pass is used on only 1 layer. All other layers are standard 193nm dry patterns, even 248nm for many metal layers. You're correct that they are capacity limited right now as fabs come online, but it has nothing to do with double patterning. In fact, double patterning is just as fast (or slow) as immersion litho, and quite a bit cheaper, so everyone will be subject to these timing constraints when they migrate to it.

Next, Low-K Interlayer Dialectrics and Hi-K/Metal Gate have really nothing to do with each other. In fact, BOTH will be (are) implemented in Intel's 45nm and IBM's/AMD's 32nm process. Intel definately uses Low-K dialectrics for the metal layers, it's just not trumpeted as much as the other camp. The reason you use low-k ILD's is to either mitigate cross-talk between metal interconnects or to be able to reduce interconnect feature size with the same relative cross-talk (or some combo of both). Considering that AMD actually has MORE metal layers than Intel I am curious as to how good their Low-K solution is.

High-K/Metal gate is a method to physically increase the thickness of the Transistor gate dialectric, while electrically making it thinner. Semi companies have reached the physical limit of gate oxide scaling for SiO2 (about 1nm) and will not be able to decrease it any further without significant gate leakage problems. A high-K dialetric now allows the industry to further scale down the gate stack dimensions for performance and reducing the effects of leakage and tunneling.

It is also unclear if IBM/AMD will use SOI or Bulk silicon processing when they transition to High-K/Metal gate although they will likely forgo SOI and move to Bulk since it should be "easier" and cheaper.

True.

This article at Semiconductor.net puts a clear picture :

http://www.semiconductor.net/article/CA6464480.html

The feedback is worth a read:

One of the major differences between the SOI and Bulk technology for the 45nm and beyond is to control the electostics or the short channel effects. For the bulk technology used by Intel the quantum confinement of carriers is controled by a combination of Hallow source/drain implant, and retrograded channel/substrate doping.

On the other hand, for the SOI technology the quantum confinement of carries in inversion layer is carried out by physically reducing the SOI thickness, Tsoi by narrowing the space between the gate oxide and the buried oxide. To mitigate the short channel effects, 45nm SOI may require 50nm~40nm Tsoi, 30nm~20nm Tsoi for 32nm, and 10nm or less Tsoi for 22nm technology. Such a thin Tsoi causes significant carrier mobility degradation and increase in threshold voltage, Vt. Furthermore, for the scaled devices, the strain induced mobility enhancement techniques become less effective. This is particularly more so for the thin SOI technology simply because in such a thin ~10nm junction and isolation depths, and channel inversion layer thickness it is extremely difficult to implement GeSi S/D junctions and a large lattice mismatch induced by the relaxed Ge-Si substrate in the channel.

Even for the 45nm SOI technology, the manufacturability of the strain induced mobility enhancement techniques used for 95nm and 65nm may not be feasible. In this respect, the SOI technology for the 45nm and beyond has a significant disadvantage over the bulk technology.

IBM and AMD are at the crossroad today to determine extenderability as well as manufacturability of the SOI technology for 45nm and beyond. The conversion from the SOI to the bulk 45nm technology node has enormous technological and manufacturability challenges. This is because IBM and AMD do not have the required learning experiences such as process, design, reliability and device yield gained from the 95nm and 65nm bulk technology development and mannufacturing.

Furthermore, two major new materials were introduced in the bulk 45nm technology: the thermal oxide, SiO2 that was used for 40 years is replaced by HfO2, and the polysilicon gate that was used for over 30 years is replaced by the metal gate. Today Intel is the only company that is manufacturing the bulk 45nm. If that is true, Intel has enormous advantages over its competitors, particularly if IBM and AMD have to adopt the 45nm bulk technology.

This is because Intel must have resolved most of the device, process, reliability, and manufacturability issues as a result of introduction of the new materials and processes. When the new materials and processes like HfO2, metal gate, and their new processes are introduced, new or unknown faiure mechanisms will be also introduced. Therefore, it is crucial to design test structures so as to bring out the unknown failure mechanisms for early detection, and develop effective E-test and reliability test screens. Such experiences gained through the 95nm and 65nm bulk technology development cycles will give an edge to Intel in successful development of the 45nm technology and beyond.

http://www.semiconductor.net/index.a...A6464480#69173