unlocking the new Athlons/Durons/thortons

[saaya]

i have not found a way to unlock them, this thread is dedicated to people who want to help me and others to find a way to unlock the recent multiplier/fsb/cache lock.

ok, i will start with the cache and the relating L2 (andL9) bridges first. here is the 1st LAYER of the L2/L9 circuit of my locked duron 1.4ghz

[Holst]

I have a 1.6gig duron on the way for a friends system.. ill be planning on clocking it so ill see what I can do midweek once the chip arrives.

[saaya]

well in case amd changed the bridges slightly, or cut them in a way that they are always shorted, no matter how you bypass them, you can cu the trace comming from and leading to the cut and connect them directly.

[Vlad Draculea]

weeeeee! i have just fuggered like 200 of my own posts, halfway to it baby.

[saaya]

i will check the circuit of the multis next, the duron died when i removed the entire first layer of the L2/L9 bridges a few hours ago

[saaya]

ok, making a drawing of the multiplier circuit (layer1) now.

have you guys noticed that except for the left L9 bridge all of the L9 bridges go back to a pin? so maybe enabling the L9 bridges will make the cache controlable via the pins? something amd originally planned, but always locked afterwards?

this could have been plannes for compability purposes originally, like a mainboard that doesnt support barton cpus could tell the cpu to run with only 256kb cache so it would work... just an idear, i dont see what the L9 bridges should be good for if not for that...

has anybody tried cutting a bridge? if the cpus would really be core locked as a lot of people claim, then it wouldnt make a diference right? i dont think they are core locked. if the core would have a lock, then it must be there since the first tbreds probably since the first palominos. but if they had that lock all the time ehy did they spend all the workforce to change the package again and again to keep people from unlocking and overclocking the cpus rather than just enable the lock?

i think it has to do with the package...

[saaya]

all traces leaving the image are going straight to the core. i will take off the little black chips and check the second layer tomorrow. hope you guys can make use of it.

[Kobalt]

just keep on commin' on. we'll figure it out someday. even if it means removing a layer of the pcb modding it and putting it back on LOL.

[sjohnson]

saaya - how are you removing the substrate to expose the circuits? Sounds like fun, I have a dead 1700+ and a nice stereo-microscope here.

[saaya]

first i used a razor knife, but then i switched to small grid sand paper, much faster

you can remove the first layer of epoxy with some chemicals, but its not worth it if you ask me...

according to ita from fab51 you could change the L2 cache size of unlocked chips via the multis, if you connect all L9 bridges. i bet it wont work, but ill give it a try anyways

ive got a feeling that amd either used some new pins that were labeled as nc till today, or maybe even uses a vcc pin as a signal pin now, to make it harder for us to find the new pin(s)

or its only the package... wich would make most sence, since amd has been working on the package for months now... and it would be a lot easier to do that change or use new pins for a lock...

dude it would be great if you could make a drawing of the circuits of that cpu or post pics!!!

[saaya]

hmmm i got some very interesting results when i meassured the resistance between the pins of the black chips!

all the pins on the core side have no resistance to each other.

the right pin of the chip of the L2 bridge leading to the right L2 bridge wich controls the L2 cache size and is cut on durons and throtons reads no resistance the any of the core sided pins either!

how do i read the values? :P
if i set my multi to read resistance and set it to 2000, does it mean the actual resistance is the number on the display x 2000

EDIT: the black chips are resistors it seems. whe i set my multimeter to read resistances and 2000 i get 998 from each pin to its counterpin. so if the resistance between a pin and its counterpin of the black chips is smaller than 1000 the two pins are connected somewhere else right?

according to ita from fab51 1kohm resistance results in less than 1v when the cpu boots up, and is interpreted as a 0 or no connect.

this makes sence, all the pins have a resistance of 1000 ohm to their counterpin, wich means they are disconnected, unless the bypass, the bridges, are connected and reduce the resistance to around 350 ohm. if the bridges are connected the resistance between the pins drops and the voltage rises above 1v and will be interpreted as a "1". if the bridges are connected the 1k ohm resistance reduces the voltage to under 1v wich is then interpreted as a "0".

when the black chips where still connected to the bridges i meassured this on them:
(multi set to resistance / 2000 ohm black-cable=ground on the pin that points away from the core)

from right to left:

0 ohm
184 (174when i switched the cables of the multimeter)
186 (178 when i switched the cables of the multimeter)
990

the L2 bridges the pins lead to (from right to left) were :

cut - connected - connected - cut

[PooSlice]

I hope you will suceed would be awsome. Keep up your work

[saaya]

all the L2 bridges on my 1700+ are closed, and i get a resistance of 204 (multi set to read resistance /2000) between all the legs of the black chip and their counterpins!

220 for the connected bridges and 990 for the pins connected to cut bridges.

i meassured the voltages on my duron on diferent spots while it was running:

black chip of the L2/L9 bridge: all pins read 0.014v , except for the pins that lead to the connected L2 bridges, they had around 0.32v running through them. i expected more :/

btw, all golden spots, triangles, the bridge names etc read 0.014v ....

hmmmm the trace of the right L2 bridge runs like this:

core -> right L2 bridge -> 1Kohm resistance -> vss?

(im pretty sure its comming from the core ,or its only running under the core, but i dont think so)

so cutting the trace that leads to the core and connect it to vss with a resistance inl line should work?

i will try to enable the cache, and not mess with the multis atm, since its a cluster of bridges and as you can see from my drawing is extremely messed up. the cache bridge is build up extremely simple, there are 4 traces to the core, each can be set to 1 or 0 by cutting the appropiate bridge or, assuming the L9 bridges are connected, by the mainboard by connecting AD8 AF8 AH8 AF6 to some current or grounding them.

[saaya]

hmmm, i will bypass the entire L2 bridge array on my 1600 tomorrow, and connect the traces leading to the cpu with vss and vcc with a 300 ohm variable resistor in line.

wish me luck!

if this doesnt work the cpus are either locked inside the core (seems more and more likely to me the longer i think on it) or they have a mechanism to ignore the external signals, maybe we need to short some pins or connect some pins to disable that lock and be able to access the multiplier cache again.

[YoupY]

First of all I'm pretty sure AMD did not locked the barton inside the core. The main reason I'm thinking this is because there are steppings which are the same between locked en unlocked procs (aqzea)

Maybe you could be on to something with those resistor packs. I have done some measuring on them before en these are the values.

fist the pic for clarification


Now some numbers. I just completed measuring the resistancepack. From top to bottom in the pic:

Pack 1 -- Top
Unlocked______Locked
1002_________998
996__________1001
905__________977
904__________980

Pack 2 -- Middle
unlocked______Locked
902__________955
898__________956
903__________951
1003_________1003

Pack 3 -- Bottom
unlocked______Locked
900__________958
905__________963
918__________976
900__________973

All these values are in ohms. I know the resistorpacks are somehow related to the bridges. Maybe the lower values result in a logic 0 and the higher values to a logic 1, which are interpreted by an mp chip.

maybe this is also comes in handy. A nice hi-res pic of the barton . Way more usefull than looking through a magnifing glass. HI-RES PIC

[saaya]

youpy, the lock could have been integrated to the core from the beginning of the palomino, but they never enabled it... and now they want to push people to move to the a64, so they enabled it all the sudden. there would have been no need to make a new revision of the core and they wouldnt change the stepping name of course, so people dont know exactly whther a cpu is locked or not from the stepping name.

[Tedinde]

These new locked chips suck. Glad I stocked up on onder tbred 1700's when it was looking like this was going to happen. About 5 new, and the 8 in my folding@home farm.

Newegg has some mobile 1700xp's 1.25 volts.

Pic looks like the normal tbred, before the new PCB crap.


http://www.newegg.com/app/viewProduc...3&searchdepa=0

[saaya]

looks good! and with one cut they are desktop chips

how much do they cost?

[Duronbird]

Tedinde, AIRGA0231WPDW ???

[saaya]

mobile...

[sjohnson]

saaya - your pm box is full. I've developed a fairly severe allergic reaction to something that will require medical attention. Don't wait on me for 1700+ circuits. Sorry

[Kobalt]

feel better!...

[Geforce4ti4200]

yea it sucks there now locked. cant you still buy one used from someone upgrading his machine though?

[Tedinde]

$58 from newegg. Havnt searched anywhere else. I miss those Mid $45 1700XP's bad!!!

[sjohnson]

saaya,

I'm sanding the dead 1700+ now. Down to the copper "ground plane" without seeing any traces. Did I go to far or do I need to sand some more. Using 600 grit. Hard to tell, this is a "brownie" and not the translucent "greenie".