Whether it's the fault of Intel memory controllers, Micron or both... I dont know. I think it's a little comparable to timings in general and auto settings (without SPD/EPP reading). If you OC RAM a little bit with auto settings some semi timings are set very very high because it's specified by JEDEC/whatever formula for x timing at y Mhz. At least, I thought some timings worked like that. Not sure. I think tRC is an example. At auto it's all the way up at 45, but 11 would work as well.

So maybe at x Mhz the auto settings for ODT and drive strenths are applied a lot stronger because Mhz decreases the signal strength a little, but this might be after all completely unnecesairy.

As I said before, Ive really no clue how exactly things work regarding IC's etc, but maybe that's an answer why Microns die en masse with certain Intel boards.