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Thread: **Official DFI LanParty UT X48-T2R(and LT) Discussion

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  1. #10
    Xtreme Member
    Join Date
    Nov 2007
    Location
    San Jose, California
    Posts
    178
    very nice info clunk, read that whole thread

    I also saw your review of the board with the geil black dragons (2gbx2). Anything past 3.6Ghz lands me either into code 1 with OCCT or corruption/firefox crashes. Would that be the RAM timings? I have gotten it to boot into windows up to 4.1 though. Any suggestions for 3.9+ stable?

    Q6660
    dfi x48
    G.Skill pc8000
    edit: I am occt stable for 30+ but not occt and prime for longer than 4 minutes ;(
    Code:
    CPU Feature Page
    Thermal Management Control................Disabled
    PPM (EIST) Mode...........................Disabled
    Limit CPUID MaxVal........................Disabled
    CIE Function..............................Disabled
    Execute Disable Bit.......................Disabled
    Virtualization Technology.................Disabled
    Core Multi-Processing.....................Enabled
    
    Main BIOS Page
    Exist Setup Shutdown......................Mode 1
    Shutdown After AC Loss....................Enabled
    O. C. Fail Retry Counter..................0
    CLOCK VC0 Divider.........................Auto
    CPU Clock Ratio...........................9x
    CPU Clock.................................416 MHz
    Boot Up Clock.............................Auto
    DRAM Speed................................333/800
    PCIE Clock................................105 MHz
    PCIE Slot Config..........................1X 1X
    
    CPU Spread Spectrum.......................Disabled
    PCIE Spread Spectrum......................Disabled
    SATA Spread Spectrum......................Disabled
    
    Voltage Setting Page
    CPU VID Control...........................1.475V
    CPU VID Special Add.......................100.23
    DRAM Voltage Control......................2.1V
    SB Core/CPU PLL Voltage...................1.10V
    NB Core Voltage...........................1.555V
    CPU VTT Voltage...........................1.453V
    VCore Droop Control.......................disabled
    Clockgen Voltage Control..................3.45V
    GTL+ Buffers Strength.....................Strong
    Host Slew Rate............................Weak
    GTL REF Voltage Control...................Disabled
    CPU GTL1/3 REF Volt.......................133
    CPU GTL 0/2 REF Volt......................122
    North Bridge GTL REF Volt ................102
    
    DRAM Timing Page
    Enhance Data Transmitting.................Fast
    Enhance Addressing........................Fast
    T2 Dispatch...............................Enabled
    Clock Setting Fine Delay..................Listed Below
    CAS Latency Time (tCL)....................5
    RAS# to CAS# Delay (tRCD).................5
    RAS# Precharge (tRP)......................3
    Precharge Delay (tRAS)....................15
    All Precharge to Act......................4
    REF to ACT Delay (tRFC)...................48
    Performance Level.........................8
    Read Delay Phase Adjust...................Listed Below
    MCH ODT Latency...........................2
    Write to PRE Delay (tWR)..................14
    Rank Write to Read (tWTR).................11
    ACT to ACT Delay (tRRD)...................3
    Read to Write Delay (tRDWR)...............8
    Ranks Write to Write (tWRWR)..............4
    Ranks Read to Read (tRDRD)................5
    Ranks Write to Read (tWRRD)...............4
    Read CAS# Precharge (tRTP)................3
    ALL PRE to Refresh........................4
    
    Read Delay Phase Adjust Page
    Channel 1 Phase 0 Pull-In.................Enabled
    Channel 1 Phase 1 Pull-In.................Enabled
    Channel 1 Phase 2 Pull-In.................Enabled
    Channel 1 Phase 3 Pull-In.................Enabled
    Channel 1 Phase 4 Pull-In.................Enabled
    
    Channel 2 Phase 0 Pull-In.................Enabled
    Channel 2 Phase 1 Pull-In.................Auto
    Channel 2 Phase 2 Pull-In.................Enabled
    Channel 2 Phase 3 Pull-In.................Enabled
    Channel 2 Phase 4 Pull-In.................Enabled
    
    Clock Setting Fine Delay Page
    Ch1 Clock Crossing Setting................More Aggressive
    DIMM 1 Clock fine delay...................Current 89ps
    DIMM 2 Clock fine delay...................Current 456ps
    DIMM 1 Control fine delay.................Current 534ps
    DIMM 2 Control fine delay.................Current 289ps
    Ch 1 Command fine delay...................Current 801ps
    
    Ch2 Clock Crossing Setting................More Aggressive
    DIMM 3 Clock fine delay...................Current 89ps
    DIMM 4 Clock fine delay...................Current 400ps
    DIMM 3 Control fine delay.................Current 367ps
    DIMM 4 Control fine delay.................Current 356ps
    Ch 2 Command fine delay...................Current 801ps
    
    Ch1Ch2 CommonClock Setting................More Aggressive
    
    Ch1 RDCAS GNT-Chip Delay..................Auto
    Ch1 WRCAS GNT-Chip Delay..................Auto
    Ch1 Command to CS Delay...................Auto
    
    Ch2 RDCAS GNT-Chip Delay..................Auto
    Ch2 WRCAS GNT-Chip Delay..................Auto
    Ch2 Command to CS Delay...................Auto
    Last edited by Rinaun; 04-20-2008 at 02:53 PM.

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