**Official DFI LanParty UT X48-T2R(and LT) Discussion

[Rinaun]

Greetings all,

Can't seem to get my X48, Q6600, or G.Skill PC28000 2gbx2 stable at anything past 3.6 on 333/800, or anything reasonable on 333/677. I know the chip can boot into windows at 4.2, and the memory clocks to around 1030. Would I use 333/667? When I do get anything remotely stable, I have corruption on downloads and random crashes in small applications (Firefox, pidgin), but they can OCCT for 30 min+.


Here are my current settings I'm using to achieve 3.6 barely stable.

CPU Feature Page
Thermal Management Control................Disabled
PPM (EIST) Mode...........................Disabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Disabled
Execute Disable Bit.......................Disabled
Virtualization Technology.................Disabled
Core Multi-Processing.....................Enabled

Main BIOS Page
Exist Setup Shutdown......................Mode 1
Shutdown After AC Loss....................Enabled
O. C. Fail Retry Counter..................0
CLOCK VC0 Divider.........................Auto
CPU Clock Ratio...........................8x
CPU Clock.................................450 MHz
Boot Up Clock.............................Auto
DRAM Speed................................333/800
PCIE Clock................................100 MHz
PCIE Slot Config..........................1X 1X

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled
SATA Spread Spectrum......................Disabled

Voltage Setting Page
CPU VID Control...........................1.4V
CPU VID Special Add.......................Auto
DRAM Voltage Control......................2.1V
SB Core/CPU PLL Voltage...................1.510V
NB Core Voltage...........................1.504V
CPU VTT Voltage...........................1.327V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Weak
GTL REF Voltage Control...................Disabled
CPU GTL1/3 REF Volt.......................N/A
CPU GTL 0/2 REF Volt......................N/A
North Bridge GTL REF Volt ................N/A

DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Enabled
Clock Setting Fine Delay..................Listed Below
CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................3
Precharge Delay (tRAS)....................15
All Precharge to Act......................4
REF to ACT Delay (tRFC)...................48
Performance Level.........................8
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................2
Write to PRE Delay (tWR)..................14
Rank Write to Read (tWTR).................11
ACT to ACT Delay (tRRD)...................3
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............4
Ranks Read to Read (tRDRD)................5
Ranks Write to Read (tWRRD)...............4
Read CAS# Precharge (tRTP)................3
ALL PRE to Refresh........................4

Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Enabled
Channel 1 Phase 1 Pull-In.................Enabled
Channel 1 Phase 2 Pull-In.................Enabled
Channel 1 Phase 3 Pull-In.................Enabled
Channel 1 Phase 4 Pull-In.................Enabled

Channel 2 Phase 0 Pull-In.................Enabled
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Enabled
Channel 2 Phase 3 Pull-In.................Enabled
Channel 2 Phase 4 Pull-In.................Enabled

Clock Setting Fine Delay Page
Ch1 Clock Crossing Setting................More Aggressive
DIMM 1 Clock fine delay...................Current 89ps
DIMM 2 Clock fine delay...................Current 456ps
DIMM 1 Control fine delay.................Current 534ps
DIMM 2 Control fine delay.................Current 289ps
Ch 1 Command fine delay...................Current 801ps

Ch2 Clock Crossing Setting................More Aggressive
DIMM 3 Clock fine delay...................Current 89ps
DIMM 4 Clock fine delay...................Current 400ps
DIMM 3 Control fine delay.................Current 367ps
DIMM 4 Control fine delay.................Current 356ps
Ch 2 Command fine delay...................Current 801ps

Ch1Ch2 CommonClock Setting................More Aggressive

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

Any help appreciated, as I have a sweet WC setup and want to hit 4

edit: I also have tinkered a bit with gtls, and maybe that was one of the reasons I hit 4.2 and posted one time. Any recommendations for 4.0-4.2ghz gtls and corresponding vtt?

double edit: I am no longer even stable at 3.6 for long periods, ater a while I get app crashes then bsod.