Phenom 9500 w/ MSI K9A2 Platinum

[Brother Esau]

Thats usually my first official move with a new chip The answer is yes they do clock under volting because if it didn't I was not gonna keep it because my 9600 BE that I just got did 2.4ghz @1.23v and 2.5ghz @ 1.25v

So as it appears I get better then the same with this chip at lower voltage then 9600 BE

[KTE]

I tried AMD Auto Clock =>
What it does is, full load your system + 1.33GB RAM, checking it for load instabilities and after a while stable, within 10ms it drops load, empties RAM, increases HT Ref. by 1MHz, thus your overall clocks and ramps load back up. It keeps going until it finds an instability (usually a freeze);
i.e., if it starts at 200x14.5 2900 and it gets past 3011MHz on your clocks, it changes multi to next one up [where possible].

It gave me 204x15 3060MHz full load stable, 205 failed [I'll catch ss next time and post it later] - voltage was 1.460v ID / 1.440v LD, creates very high load

Here's it working half way, going up from 2800/2200




But the cold facts are, whilst that much I've already had software load stable many times before, it is still not stable during idle/WISE, hence unstable

KTE: I actually havn't updated Everest in a while, and I just did. Now its giving me All 4 cores and CPU temp, before it was just CPU. Which one should I go by? CPU or Core? Thanks

Both, one diode is a pin diode + offset + BIOS/application offset (same as you see in BIOS usually) and the other is from many Tjunction CPU/IMC diodes as one sensing feedback. Use the "Core" ones to check temps because its linked to the TCC - personally I would advise to stay below 75C full load in it with 9850BE/9750/9100 but the actual Tctl_max limit is 115.5C on these CPUs before throttling or damaging temperature is reached [i.e. Tcase_max]. The register checks confirm what I know from AMD previously too when I complained about how low the Max rated temp was (assuming it was 70C).

Whats PTuner? Is that Motherboard Specific Software?

Like SocketMan says
Accurate if you can have it calibrated against known measurements. Voltages tend to be off due to measurement point [source rather than end terminals - so there's a loss (-) to add].

It's software that comes with Gigabyte GT Power supplies
Speaking of which does the 550w version have the voltage increase slider?(see pic)

Yep, same thing.

KTE maybe your WISE instabilities are caused by something other then the CPU, like a video card/ram/ (hopefully not) motherboard (as I just got one) or a combination of the above?

Its not RAM/GPU, since I have X2/Intel systems that I've checked them in. If its MB, I'm not sure. You have the MSI?

KTE

Initial tests of P0J over 141 show the following.

Boot with Autoxpresss enabled brings on Yellow in AOD
Winrar scores are slightly higher than 141 as long as I set red in AOD
cinebench no different either yellow or red

I will continue to test, as for now I think 141 is the same bios with autoxpress just hidden ( I will recheck with amibcp)

I hit the same clocks, get the same ram speeds and the same bandwidth with both, even in everest.

Remember im using 4GB 2x2 in vista 64 vanilla, 5-5-5-15-11 1000mhz

T

Hmm.. Tony I've no idea what is happening. I'm on P0J, much lower than you in MHz, but here's the scores I have [AOD yellow]



My CB10 trend is same as yours and so is WinRAR [with AOD buttons]
Green is no go, low perf.

I'll post 500 5-5-5-15-11 scores after this with 2x1GiB.

Mathos, you can get lower than 0.8v on B2/B3 if you drop clocks enough. We've had 0.4xv pretty easily. 0.8v is lowest rated per the CnQ rated spec, which is 1GHz lowest, if you go below it, which is easily possible, you'll be able to drop below. For K10 lowest and upper CPU/NB voltage boundaries (Serial and Parallel for VRMs) are <very low> to 1.550. See BKDG. Can I ask how you know 0.8-1.4v is the Phenom design limit?


Just checked 9850BE capabilities encoded within CPU [look at them carefully ]:

MP capability -> F3xE8 [18:16] = 111b = 1 processor max supported
DdrMaxRate -> F3xE8 [7:5] = 100b = 800 MT/s max supported
L3Capable -> F3xE8 [25] = 1b = L3 present
DiodeOffset -> F3xE4 [7:5] = 30h = +11C

MaxNbFid: maximum NB COF -> MSRC001_0071 [63:59] = 00h = unlimited
MinVid: minimum voltage -> MSRC001_0071 [63:59] = 00h = unlimited
MaxVid: maximum voltage -> MSRC001_0071 [41:35] = 00h = unlimited

[current] MemClkFreq -> F2x[1, 0]94 [2:0] = 011b = 400MHz (DDR2-800)
[This field specifies the frequency of the DRAM interface (MEMCLK) - DDR3-1600 is already supported by K10h]

ECX 23:16 L1 data cache associativity = 2
ECX 15:8 L1 data cache lines per tag = 1
EDX 23:16 L1 instruction cache associativity = 2
EDX 15:8 L1 instruction cache lines per tag = 1
EDX 6 100MHzSteps: 100 MHz multiplier Control = 1
EDX 5 STC: software thermal control (STC) is supported
EDX 4 TM: hardware thermal control (HTC) is supported
EDX 3 TTP: THERMTRIP is supported = 1
EDX 2 VID: Voltage ID control is supported = 0 (function replaced by HwPstate).
EDX 1 FID: Frequency ID control is supported = 0 (function replaced by HwPstate).
EDX 0 TS: Temperature sensor = 1.

IddDiv: current divisor field -> MSRC001_0068 Current P-State [41:40] = 01b = IddValue / 10 A
IddValue: current value field -> MSRC001_0068 Current P-State [39:32] = EEh = 238 / 10 A = 23.8A per core
Loadline Vdd = 1.376v

Stock 9850BE: 4*(1.280*23.8) = 122W max power
OC 2800/2200: 4*(1.376*23.8) = 131W max power

HtcPstateLimit: HTC P-state limit select -> F3x64 [30:28] = 001b = P-State 1
[Specifies the P-state limit of all CPU cores when in the HTC-active state]

CurTmp: current temperature -> F3x64 [31:21] = 22h = 34C Tctl

HtcTmpLmt: HTC temperature limit -> F3x64 [22:16] = 01111111b = 127
(F3x64 is not accessible if F3xE8[HTC capable]=0)

9850BE HTCTmpLmt: 52.0 + (0.5 * 127) = 115.5C (Sandra >)



HtcHystLmt: HTC hysteresis -> F3x64 [27:24] = 00000010b = 2
[The processor exits the HTC-active state when Tctl is less than HtcTmpLmt minus HtcHystLmt]

9850 exits HTC-active below; 115.5 - 2 = 113.5C

TmpMaxDiffUp: temperature maximum difference up -> F3xA4 [6:5] = 00b = Upward slewing disabled
[if the measured temperature is detected to be greater than Tctl then Tctl is updated to match the measured temperature]

TmpSlewDnEn -> F3x64 [7] = 1h = Slew rate controls in the downward direction are enabled
[0=Downward slewing disabled; if the measured temperature is detected to be less than Tctl then Tctl is updated to match the measured temperature. BIOS should set this bit to 1]

2.10 Thermal Functions
Thermal functions HTC, STC and THERMTRIP are intended to maintain processors temperature in a valid
range by:
• Providing an input to the external circuitry that controls cooling.
• Lowering power consumption by switching to lower-performance P-state or.
• Sending processor to the THERMTRIP state to prevent it from damage.
The processor thermal-related circuitry includes (1) the temperature calculation circuit (TCC) for determining
the temperature of the processor and (2) logic that uses the temperature from the TCC. The processor includes
a thermal diode as well.

2.10.1 The Tctl Temperature Scale
Tctl is the processor temperature control value, used by the platform to control cooling systems. Tctl is accessible through SB-TSI and F3xA4[CurTmp]. Tctl is a non-physical temperature on an arbitrary scale measured in degrees. It does not represent an actual physical temperature like die or case temperature. Instead, it specifies the processor temperature relative to the point at which the system must supply the maximum cooling for the processor’s specified maximum case temperature and maximum thermal power dissipation. It is defined as follows for all parts:
• For Tctl = 0 to Tctl_max - 0.125: the temperature of the part is [Tctl_max - Tctl] degrees under the temperature for which maximum cooling is required.
• For Tctl = Tctl_max to 255.875: the temperature of the part is [Tctl - Tctl_max] degrees over the worst-case expected temperature under normal conditions. The processor may take corrective actions that affects performance or operation as a result, such as invoking HTC or THERMTRIP_L.

2.10.2 Thermal Diode
The thermal diode is a diode connected to the THERMDA and THERMDC pins used for thermal measurements.
External devices use measurements from the thermal diode measurements to calculate temperature during operation and test. These measurements are required to be adjusted as specified by F3xE4[DiodeOffset].
This diode offset supports temperature sensors using two sourcing currents only. Other sourcing current implementations are not compatible with the diode offset and are not supported. A correction to the offset may be required for temperature sensors using other current sourcing methods. Contact the temperature sensor vendor to determine whether an offset correction is needed.

2.10.3 Temperature-Driven Logic
The temperature calculated by the TCC is used by HTC, STC, THERMTRIP, the PROCHOT signal.

2.10.3.1 PROCHOT_L and Hardware Thermal Control (HTC)
The processor HTC-active state is characterized by (1) the assertion of PROCHOT_L, (2) reduced power consumption, and (3) reduced performance. While in the HTC-active state, the processor reduces power consumption by limiting all CPU cores to a P-state (specified by F3x64[HtcPstateLimit]). See section 2.4.2 [P-states] on page 31. While in the HTC-active state, software should not change F3x64 (except for HtcActSts and HtcEn).
Any change to the previous list of fields when in the HTC-active state can result in undefined behavior. HTC status and control is provided through F3x64.
The PROCHOT_L pin acts as both an input and as an open-drain output. As an output, PROCHOT_L is driven low to indicate that the HTC-active state has been entered due to an internal condition, as described by the following text. The minimum assertion and deassertion time for PROCHOT_L is 15 ns.
The processor enters the HTC-active state if all of the following conditions are true:
• F3xE8[HtcCapable]=1
• F3x64[HtcEn]=1
• PWROK=1
• THERMTRIP_L=1
• The processor is not in the C3 ACPI state.
and any of the following conditions are true:
• Tctl is greater than or equal to the HTC temperature limit (F3x64[HtcTmpLmt]).
• PROCHOT_L=0
The processor exits the HTC-active state when all of the following are true:
• Tctl is less than the HTC temperature limit (F3x64[HtcTmpLmt]).
• Tctl has become less than the HTC temperature limit (F3x64[HtcTmpLmt]) minus the HTC hysteresis limit (F3x64[HtcHystLmt]) since being greater than or equal to the HTC temperature limit (F3x64[HtcTmpLmt]).
• PROCHOT_L=1.
The default value of the HTC temperature threshold (Tctl_max) is specified in the Power and Thermal Datasheet.

2.10.3.2 Software Thermal Control (STC)
STC is controlled by [The Software Thermal Control (STC) Register] F3x68. This register provides a software-controlled mechanism to alter power consumption based on temperature. When the processor control temperature (Tctl; see section 2.10.1 [The Tctl Temperature Scale] on page 110) exceeds the temperature threshold specified by F3x68[StcTmpLmt], then the processor enters the STC thermal zone. When it subsequently drops below F3x68[StcTmpLmt] minus F3x68[StcHystLmt], the processor exits the STC thermal zone. F3x68 controls whether interrupts or special bus cycles (which may be converted into interrupts by the chipset) are generated when the processor transitions into and out of the STC thermal zone. The interrupt handler may take an action to alter power consumption or alter the level of external cooling.
One way that software may reduce power is to program the processor to enter the STC-active state. This is like the HTC-active state, however PROCHOT_L is not asserted. The processor enters the STC-active state if F3x68[StcPstateEn]=1. While in the STC-active state, the processor limits the performance to the P-state specified by [The Software Thermal Control (STC) Register] F3x68[StcPstateLimit]; See section 2.4.2 [P-states]
on page 31.

2.10.3.3 THERMTRIP
If the processor supports the THERMTRIP state (as specified by [The Thermtrip Status Register] F3xE4[ThermtpEn] or CPUID Fn8000_0007[TTP], which are the same) and the temperature approaches the point at which the processor may be damaged, the processor enters the THERMTRIP state. The THERMTRIP function is enabled after cold reset (after PWROK asserts and RESET_L deasserts). It remains enabled in all other processor states, except during warm reset (while RESET_L is asserted). The THERMTRIP state is characterized as follows:
• The THERMTRIP_L signal is asserted.
• Nearly all clocks are gated off to reduce dynamic power.
• A low-value VID is generated.
• In addition, the external chipset is expected to place the system into the S5 ACPI state (power off) if THERMTRIP_L is detected to be asserted.
A cold reset is required to exit the THERMTRIP state.

The processor measures temperature to 1/2-degree C resolution. However, temperature is reported through Tctl with 1/8th-degree resolution. The translation to finer resolution is accomplished using slew rate controls in this register. These specify how quickly Tctl steps to the measured temperature in 1/8th-degree steps. Separate controls are provided for measured temperatures that are higher and lower than Tctl. The per-step timer counts as long as the measured temperature stays either above or below Tctl; each time the measured temperature flops to the other side of Tctl, the step timer resets. If, for example, step times are enabled in both directions, Tctl=62.625, and the measured temperature keeps jumping quickly between 62.5 and 63.0, then (assuming the step times are long enough) Tctl would not change; however, once the measured temperature settles on one side of Tctl, Tctl can step toward the measured temperature.

Also it seems NB Speed can also be dropped in low power states using DID (?):

F3xD4 [30:28] NbClkDiv: NB clock divisor. Read-write. Cold reset: value varies by product.
Specifies the NB CLK divisor associated with [The ACPI Power State Control Registers] F3x[84:80][NbLowPwrEn]. This divisor is applied while LDTSTOP is asserted if the corresponding core CLK divisor, F3x[84:80][ClkDivisor], is set to “turn off clocks” or if NBClkDivApplyAll=1; otherwise, the divisor specified by F3x[84:80][ClkDivisor] is applied. This divisor is relative to the current NB FID frequency, or:
• 200 MHz * (4 + F3xD4[NbFid]).
If MSRC001_00[68:64][NbDid] of the current P-state indicates a divisor that is lower than specified by this field, then no NB frequency change is made when entering the low-power state associated with this register (i.e., if this field specifies a divide-by 1 and the DID is divide-by 2, then the divisor remains 2 while in the low-power state). This field is encoded as follows:
Bits Divisor Bits Divisor
000b Divide-by 1. 100b Divide-by 16.
001b Divide-by 2. 101b Reserved.
010b Divide-by 4. 110b Reserved.
011b Divide-by 8. 111b Reserved.
BIOS should set this field to 100b

2.9.2 CPU Cores and Downcoring
Each node supports 1, 2, 3, or 4 CPU cores as follows:
• The number of cores supported by the node is specified by F3xE8[CmpCap].
• CPU cores may be downcored (removed) by F3x190[DisCore[3:0]] through a warm reset. This may be useful in that CPU cores that are determined to be bad may be removed from operation. Based on F3xE8[Cmp-Cap], DisCore[0] applies to a single-core node; DisCore[1:0] apply to a dual-core node; DisCore[2:0] apply to a 3-core node; DisCore[3:0] apply to a 4-core node.
• F3x190[DisCore] affects CPUID Fn8000_0008_ECX[NC].
• Software is required to use F3x190[DisCore[3:0]] as follows:
• 1, 2, 3 or 4 cores must be enabled on each node(0-core configurations are not allowed).
• Setting bits corresponding to CPU cores that are not present results in undefined behavior.
• Once a core has been removed, it cannot be added back without a cold reset.
• If the number of cores in the system is changed, then F0x60[CpuCnt] in all nodes must be updated to reflect the new value after the warm reset.
• The CPU core number, CpuCoreNum, is provided to SW running on each core through CPUID Fn0000_0001_EBX[LocalApicId] and APIC20[ApicId], formatted based on the state of MSRC001_001F[InitApicIdCpuIdLo]; CpuCoreNum also affects F0x68[Cpu1En] and F0x168[Cpu3En and Cpu2En]. CpuCoreNum, varies as the lowest integers from 0 to 3, based on the number of enabled cores;
e.g., a 4-core node with 1 core disabled results in cores reporting CpuCoreNum values of 0, 1, and 2 regardless of which core is disabled. Here are all the possible downcore combinations:
• A 4-core node with 0 cores disabled. A 3-core node with 0 cores disabled.
• A 4-core node with 1 core disabled. A 3-core node with 1 core disabled.
• A 4-core node with 2 cores disabled. A 3-core node with 2 cores disabled.
• A 4-core node with 3 cores disabled. A 2-core node with 0 cores disabled.
• A 1-core node with 0 cores disabled. A 2-core node with 1 core disabled.
• The boot core is always the core reporting CpuCoreNum = 0.
Some legacy operating systems do not support three core processors. The BIOS should support a user configurable option to disable one core in a three core processor for legacy operating system support.

Achim, have you tried limiting CPU temp using STC? (changing the value manually)

BTW, see if you can spot something incorrectly affirmed here: http://www.xbitlabs.com/articles/cpu...md-k10_10.html

Check these two articles:
http://money.cnn.com/2008/04/07/tech...tune/index.htm
http://www.eetimes.com/news/latest/s...leID=207100361

[justapost]

The memory controller manages its voltage independently of the cores and may lower the voltage in case of lower load.

M3A has an bios option that allows disabling one of the DCS's for power saving if not used. Think that's what they meant in the source the write for the article used here.
But it sounds like the NB has todaly independant power management which is wrong.

Trying "Auto Clock" here again. Does the board monitor show the currently testing "ref HT". Here it's always at 200MHz.

Did not try that STC thing. Think i must write an app handeling that interupt the STC generates if temps exceed.

[KTE]

M3A has an bios option that allows disabling one of the DCS's for power saving if not used. Think that's what they meant in the source the write for the article used here.
But it sounds like the NB has todaly independant power management which is wrong.

Hehe, you know another thing... they mention all cores have one single voltage plane, which is completely wrong. All cores can have separate voltage planes.

Trying "Auto Clock" here again. Does the board monitor show the currently testing "ref HT". Here it's always at 200MHz.

It changes perfectly with mine, exactly to what its testing - it just takes a while to change. When its running stability test, load is too high to actually flick between screens or open anything else up. It jams computer for a bit.

I just ran it again. This is what it gave me stable



Still idling unstable though

On another note, I tested 2300 1.4v and guess what? It gave the same problem, froze idling. Which means it can't be clocking/voltage related... something else.

Did not try that STC thing. Think i must write an app handeling that interupt the STC generates if temps exceed.

You can write to the register directly right?

[Oldguy932]

1.4v is too high for 2300 though, that'll cause instability by itself. You could probably get away with 1.1v, maybe even less. I can run 2.5ghz on both the cpu and nb with vCore at 1.15v and vNB at 1.25v. Right now I'm running simple stability testing to see the minimum voltage needed every 50 mhz after 2.5ghz. I only run small fft's for an hour at most and then up the speed, and I record voltages, speeds, and idle/load temps. Maybe later I can do the testing for how overclocking improves more than linear. I stopped trying for the 3ghz NB because it wouldn't stabilize at all. The most stable it got was 3 iterations into superpi 1m and then it would error. Maybe after some more burning in it'll go higher.

[maverik-sg1]

Are these cpu's workable under phase cooling (FX60 and alike were coldbugged) and how much further do they go?

[KTE]

This is where AOD Autoclock will lockup for me



maverik-sg1 yeah but only NB seems to get better under it.

[jonspd]

Tony or KTE could either of you please try 1.13 with the 9850.

[d412k5t412]

Tony or KTE could either of you please try 1.13 with the 9850.

I'm pretty sure that it will not boot up. I installed 1.2 and it didn't.

[jonspd]

1.2 is a official bios.

[KTE]

Tony or KTE could either of you please try 1.13 with the 9850.

Yes Dear

So... you're trying to get us to kill our boards or have a non boot Phenom?

Anyway.... hehehe




Shes lives!
November '07 BIOS booting B3 flawless and all oc options are in here.
Just the 1066 MEM mode problem, but who cares.

I'm pretty sure that it will not boot up. I installed 1.2 and it didn't.

You're right, it never did, I had tried earlier, so I quit - today, I felt another urge to checkup and it's booted up fine 8 times now from a CMOS clear

[d412k5t412]

You're right, it never did, I had tried earlier, so I quit - today, I felt another urge to checkup and it's booted up fine 8 times now from a CMOS clear

So 1.13 DID work? Cuz 2k on winrar is amazing for 2.5ghz and I think ill go to 1.13!!

[KTE]

It can crack plus 2.1k stock at 2500/800, my timings are very loose

[d412k5t412]

It can crack plus 2.1k stock at 2500/800, my timings are very loose

Have you tried to overclock with 1.13? If so, better results possibly?

[KTE]

Kinda.. I benched 3.1G, I am sure it could do 3.2G bench too, finished 4 runs of CB10 at 3.1G on each core but as soon as the multi-threaded one started, the amp draw on CPU 12V shot up above 18A and that tripped by PSU OCP - instant shutdown

18*11.94= 215W DC

So I can't get any more stable since this MB only takes 4-pin 12V. RAM/HT/NB will obviously be much more on this BIOS because of its options.

[justapost]

Hehe, you know another thing... they mention all cores have one single voltage plane, which is completely wrong. All cores can have separate voltage planes.

But if only one core is under load all other cores run at p-state-0 voltage. So int erms of energy efficiency i see no benefit here.

It changes perfectly with mine, exactly to what its testing - it just takes a while to change. When its running stability test, load is too high to actually flick between screens or open anything else up. It jams computer for a bit.

I tried it twice first at 2.8/2.2. AOD always sets 1.25V vcore, 1.3V VID's and 1.8V for the mem. The system started counting up ref HT and froze at ~207MHz without increasing the cpu multi.
Next time i started at 2.5/2.0 and increased vcore to 1.3 and mem voltage to 2.1V. It froze at ~13x203.
After that and the freeze after over night prime95 during sandra latency test at 2.9/2.2 1.4/1.35V i decided to take a break for today.

On another note, I tested 2300 1.4v and guess what? It gave the same problem, froze idling. Which means it can't be clocking/voltage related... something else.

I'd agree with oldguy 1.4v is unreasonable high for 2.3GHz. The freezes seem to be more higher voltage/temp related that clock speed related.

You can write to the register directly right?

What register do you mean? I understand STC like that. If the temps exceed an given point the cpu generates an special interupt. Special software is needed to do the proper action (example: switch to a lower p-state or increase the fan speed).

Hmm just one 4pin 12V connector, did not expect that. Tried a phenom in the GBT780G yet? Watch the voltages in CPU-Z! I gave the cpu an +0.025V voltage plus and had voltages from ~1.29V (idle) 1.49V (load) at 2.8/2.2GHz. .

[d412k5t412]

Kinda.. I benched 3.1G, I am sure it could do 3.2G bench too, finished 4 runs of CB10 at 3.1G on each core but as soon as the multi-threaded one started, the amp draw on CPU 12V shot up above 18A and that tripped by PSU OCP - instant shutdown

18*11.94= 215W DC

So I can't get any more stable since this MB only takes 4-pin 12V. RAM/HT/NB will obviously be much more on this BIOS because of its options.

Do you think the TLB-Patch that is applied in other BIOS, and not 1.13 is the reason for better oc/bench?

Edit: Can't even get 2.8ghz stable :'(

[Tony]

I am wondering if its because im using 4Gb with lose clocks and 2t that my winrar scores are lower.

KTE, what you seeing for L3 latency in Everest? i see between 6.2 and 5.9ns at high clocks, what you getting?

[Oldguy932]

L3 latency has alot more to do with NB speed than with CPU speed although both have an effect on it. 2.75ghz on both cpu and nb gives me 6.6ns, but with the same cpu but 2.5ghz nb it goes up to 7.2ns. Memory copy speed seems to be completely dependent on the speed of the L3, along with the read speed for the L3 being dependent on the read speed of the memory. Just wondering but whats the highest stable nb anyone's gotten here? I've gotten 2.8ghz, will be testing higher later today.

[Tony]

I'm hitting 6.2ns at 2.5ghz Nb easy, you have issues there oldguys 2.6GHZ NB brings me sub 6ns with the CPU around 3.5ghz

[Oldguy932]

My issue is that my cpu does 2.7 stable at 1.1875v, but it takes 1.325 for 2.75 to be stable. There's got to be something else going on to cause the cpu to need that much more voltage. And I actually do get 6.6ns at either 2.5 or 2.75 nb with the cpu at 2.75, my mistake. But the L3 does get faster with increased memory speed, I think I meant to say that the difference between the 400 and the 533 mem dividers gave me the difference in latency rather than the nb speed.

[Brother Esau]

2.7ghz at that voltage I would be very happy

[Oldguy932]

I might go back to that setting and burn it in some more, depends on how much voltage is needed to go up to 2.8ghz from 2.75. I personally just like having the really fast nb.

Actually I just went back to the setting and just started the auto clock in aod to see what it can do.

[KTE]

But if only one core is under load all other cores run at p-state-0 voltage. So int erms of energy efficiency i see no benefit here.

Yeah thats a downside - but for me its good to do since my CPU spends nearly all the time idling.

I tried it twice first at 2.8/2.2. AOD always sets 1.25V vcore, 1.3V VID's and 1.8V for the mem. The system started counting up ref HT and froze at ~207MHz without increasing the cpu multi.
Next time i started at 2.5/2.0 and increased vcore to 1.3 and mem voltage to 2.1V. It froze at ~13x203.
After that and the freeze after over night prime95 during sandra latency test at 2.9/2.2 1.4/1.35V i decided to take a break for today.

It means its either buggy with your OS/BIOS or you have instability problems since it loads CPU/MEM a lot.
It did not work with my 96BE so it might be just incompatibility with your system.

I'd agree with oldguy 1.4v is unreasonable high for 2.3GHz. The freezes seem to be more higher voltage/temp related that clock speed related.

Hmm... voltage at 1.4v won't have that affect on an IC if its cooled and capable of it but the reverse is true. Chip designers test this way to look at power difference at one MHz but different Vdd at the pins very regularly. I have been benching all rigs like this for a while, I have them at those volts [1.384] because I was dropping and increasing multi from 9x to 16x very regularly.

What register do you mean? I understand STC like that. If the temps exceed an given point the cpu generates an special interupt. Special software is needed to do the proper action (example: switch to a lower p-state or increase the fan speed).

Yes that's how I understand it too, register needing modification would be F3x68[StcPstateEn]=1.

Hmm just one 4pin 12V connector, did not expect that. Tried a phenom in the GBT780G yet? Watch the voltages in CPU-Z! I gave the cpu an +0.025V voltage plus and had voltages from ~1.29V (idle) 1.49V (load) at 2.8/2.2GHz. .

Kinda crazy that. I have just thrown 1.72v on my 9850 to try and bench 3.2G and avoid massive vDroop to 1.503v - ran single threaded fine, multi-threaded shutdown system through overload protection.
GBT780G never booted my Phenom. Thanks for the advice there!

Do you think the TLB-Patch that is applied in other BIOS, and not 1.13 is the reason for better oc/bench?

P0J doesn't have a patch applied b default but with a choice and all BIOSes have gone worse by the day in perf. and 113 is one of the earliest and hence, one of the best performers

I am wondering if its because im using 4Gb with lose clocks and 2t that my winrar scores are lower.

Clocked higher with higher CPU/NB/MEM, scores should be higher than mine. At 3G I've cracked 2476KB/s with a fairly low NB so I'm looking at your MEM size here. Weird though, very..

KTE, what you seeing for L3 latency in Everest? i see between 6.2 and 5.9ns at high clocks, what you getting?

L3 latency has alot more to do with NB speed than with CPU speed although both have an effect on it. 2.75ghz on both cpu and nb gives me 6.6ns, but with the same cpu but 2.5ghz nb it goes up to 7.2ns. Memory copy speed seems to be completely dependent on the speed of the L3, along with the read speed for the L3 being dependent on the read speed of the memory. Just wondering but whats the highest stable nb anyone's gotten here? I've gotten 2.8ghz, will be testing higher later today.

I'm hitting 6.2ns at 2.5ghz Nb easy, you have issues there oldguys 2.6GHZ NB brings me sub 6ns with the CPU around 3.5ghz

My issue is that my cpu does 2.7 stable at 1.1875v, but it takes 1.325 for 2.75 to be stable. There's got to be something else going on to cause the cpu to need that much more voltage. And I actually do get 6.6ns at either 2.5 or 2.75 nb with the cpu at 2.75, my mistake. But the L3 does get faster with increased memory speed, I think I meant to say that the difference between the 400 and the 533 mem dividers gave me the difference in latency rather than the nb speed.

Well, we need to be careful or we'll start getting these again
You can easily disprove false/buggy clocks with a Sandra/EVE run, like the above was when I ran EVEREST here. Look at the cache b/w as well at different clocks.

Format: HT*CPU multi*NB muti*MEM multi

I get around 6.5-6.2ns on the 9600BE at 2.5-2.58G NB, not high CPU/MEM clocks. This was one on the 9600BE



This is a standard air run by Sami back sometime near late November IIRC:


Which clock affects most=>

This is what 2.85CPU/2.19NB/876MEM gets [9850]:


Again, higher up NB but lower CPU/MEM clocks, 232*12*11*2, look at ALL bw numbers [9600]:


Now clocks are higher than above, 236*12*11*2, compare [9600]:


Lastly, NB/CPU clocks are lower than above but MEM clock much higher in 1066 mode despite the higher latencies, 235*11.5*11*2.66, [9600]:



You can see all bw/latency figures depend highly on NB Clock->1066 mode clock->CPU clock->latencies. Tighter latency is not better for Phenom, higher MEM clock is. 1250 5-5-5-15 is better than 450 3-3-3-3 1T or 500 4-4-4-4 1T in overall bws but slightly higher latency.

2.3G CPU/2.4G NB gets around 7.5ns. Haven't checked it out for 9850 properly yet.

2.7ghz at that voltage I would be very happy

Depends how long and which methods it takes you to verify stability. Will it last partner?


Anyway, one of the OSes I'm going to try these days is µ-velOSity Real-Time... real-time in MEM as it says. Anyone tried it yet?

Check this report out BTW: Intel, AMD multi-core processing approach doomed - UK multi-processing experts

[Brother Esau]

Damn you make some frigging long ass posts You on speed or something Tye