Quote Originally Posted by mrcape View Post
Interesting about P5K bios. Is that a recent change or has it been that way since 45nm launch in January?

The lowest PLL setting in the DFI bios is 1.55v. The VTT minimum I think is 1.10v or 1.12v. They added new 45nm GTL table to the bios maybe a month after 45nm on the market.
It has been that way since the bios started coming that supported 45nm. I believe 0906 was the first. 1004 and 1006 also have the same information within the bios and auto detects 45 or 65nm and adjusts accordingly. Maybe the DFI board and others are the reason why some people ARE having problems however. These boards that don't lower the PLL and VTT are just over juicing and frying 45nm chips.