Howto disable the tlb-fix with CrystalCPU

[sam2008]

@sam2008 do you wanna finish that ini-file proposal. I'd prefere to write a small gui app to modify p-states.

Spent all night working on this dann program, finally got it done. Crashed my computer several times when doing the mask debuging.



This PhenomMSR.EXE program is based on CrystalCPUID. You will need CrystalCPUID for the program to function. PhenomMSR is a free program for personal use. It is meant for studying and experimenting purposes only. The author holds NO responsibility for the consequences caused by this program. Program may not function on CPUs other than AMD Phenom (haven't tested outside Phenom). To set it up, please refer to HERE for how to properly set it up.

Use at YOUR OWN RISK!!!

Change the MSR settings in the PhenomMSR.INI file for your needs.

(1) You can read and write up to 4 MSRs at same time for all 4 cores
(2) INDEX is the address of the MSR you want to modify
(3) HIGH is the 64-33 bits of the MSR value you want to write
(4) Low is the 32-1 bits of the MSR value you want to write
(5) MASK_HIGH is the mask for 64-33 bits; MASK_LOW is the mask for 32-1 bits.
(6) If INDEX for that [MSR] is set to 0x0, the program will skip that MSR and do nothing.
(7) If MASK is set to 0x00000000, the program will directly write the values in HIGH and LOW into MSR
(8) If MASK is set to 0xFFFFFFFF, the program will basically do nothing to the original value of MSR
(9) For other cases, changing the MASK value accordingly.

Use at YOUR OWN RISK!!!

Download PhenomMSR.RAR 1.01

About the MASK
Here is the how the MASK works. If O is the original value in MSR, W is the value need to be written, and M is the mask, the logic operation is (O and M) or ((NOT M) and W).
For example, if O=01 10 00, and you want to write W=10 11 01 into the MSR but would like the 3-4 bit in the original O unchanged, then you should use M=00 11 00.
(O and M)=(01 10 01 & 00 11 00)=00 10 00
(Not M)=~ 00 11 00=11 00 11
(Not M) and W= 11 00 11 & 10 11 01=10 00 01
(O and M) or ((Not M) and W)= 00 10 00 | 10 00 01=10 10 01.
As you can see the center 2 bit as masked by M is unchanged.


[Update PhenomMSR v1.02]
Added Support for Core Masking in the INI file.
Now you can use the COREMASK to specify which core you want the MSR value to be written. It is 4-bit binary value. The lowest bit is core 1, second bit is core 2, third bit is core 3, and fourth bit is core 4. When a bit is set to 1, MSR for that core will be written. If a bit is set to zero, the program will skip the MSR for that core. For example, 0b1011 means core 1, 2, and 4 will be written, and core 3 will be skipped. If COREMASK is set to 0b1111, then the selected MSR for all four cores will be written. If COREMASK is set to 0b0000, then selected MSR won't be written to any of the cores. Changing the COREMASK value accordingly. It is set at 0b1111 by default (all 4 core enabled).


Download PhenomMSR v1.02