Quote Originally Posted by Grnfinger View Post
I run the 5:6 divider on the 333 strap @1147MHz 5-5-5-15

DRAM Static Read Control: Enabled
Ai Clock Twister : Strong
Transaction Booster : Disabled
Relax level: 1
DRAM Static Read Control:
This function is best set to "Disabled" for high FSB levels (450 FSB upwards). "Enabled" gives a small gain in memory access latency at the expense of overall stability. We believe this setting alters a single TRD phase to low; performance advantages either way are not stellar.
I've run with mine on Disabled for the longest time, since I got the Board. Tested 440-456 FSB with Enabled and Disabled and it seemed to do little for stability, seems more a performance related setting? I didn't boot into XP, I was just testing using Memtest Test 5.