Performance level of ram?

[Pain|Killer]

How can I change Performance level in bios. I mean what is it called in bios?

Will it have any impact on performance? Should i change it to 6 or 5?

I didn't try to set it in memset because i am unsure what setting it is going to change and what if it wouldn't load up windows after changing the performance level setting.

When my cpu was at 333*9=3.0Ghz, performance level was at 5. Now it is changed to 7 as i have OC my cpu to 3.2Ghz.

So please i need your assistance. Thanks.

[Zeus]

It depends on which board you have but for Asus it's called "transaction booster" , level 3 is the lowest setting for performance level, in conjuction with the strap to northbridge you select.

This performance level or transaction booster is not a memory setting but a northbridge latency setting.

The lower the PL number, the more Vmch it requires.

[before]

It depends on which board you have but for Asus it's called "transaction booster" , level 3 is the lowest setting for performance level, in conjuction with the strap to northbridge you select.

This performance level or transaction booster is not a memory setting but a northbridge latency setting.

The lower the PL number, the more Vmch it requires.

PLVLs are individually hard-coded for each memory channel. Their locations into the MemoryBaseAddress are just among DRAM timings. The tighter the Performance Level(s), the higher the vDDR.

[Zeus]

PLVLs are individually hard-coded for each memory channel. Their locations into the MemoryBaseAddress are just among DRAM timings. The tighter the Performance Level(s), the higher the vDDR.

Really?

I remember how i couldn't get PL 5 stable for 32M untill i raised Vmch, that's why i assumed it was a NB latency setting.

This feeling got strengthend by the fact that PL's are dependent on the strap to northbrige selected.

I'm not an expert, these are just my observations on this subject.

[massman]

PL = tRD

Time to read FCG's article at Anandtech, really interesting stuff: http://www.anandtech.com/mb/showdoc.aspx?i=3208&p=5

[before]

Really?

I remember how i couldn't get PL 5 stable for 32M untill i raised Vmch, that's why i assumed it was a NB latency setting.

This feeling got strengthend by the fact that PL's are dependent on the strap to northbrige selected.

I'm not an expert, these are just my observations on this subject.

Like any other DRAM timing, PLVL offsets are among the DRAM registers (highlighted in yellow here; just prior to offset 24Ah, set to 86 and which changes with tCL, CH0 tCL -here, 86 = tCL7-)



Anyway; increasing the vMCH may have as positive effect as well.

It's a matter of balance, there are offsets which stress more the MCH, and others which stress more the DRAM. For instance, on a P5B P965, if you want to run 23 setting for offset 03Fh (not in the table ) at lets say 550FSB, you need a significantly higher vMCH than with 24... But usually, if you want to decrease the PLVL, you need to increase vDDR first. At least, that's what I think to be logical by considering PLVL location into the MCHBAR.

PL = tRD

Time to read FCG's article at Anandtech, really interesting stuff: http://www.anandtech.com/mb/showdoc.aspx?i=3208&p=5

That's an interesting supposition. Anyway, I may miss something, but I'm not that sure. Or well, maybe it's a part of what we call "tRD".

In the above posted table, there are few different offsets for Read Delay, (tRD Phase Adjust, Write to Read Delay Same/Different Rank, Read to Read Delay Same/Different Rank; etc.)

[massman]

Could those other offsets for Read Delay you mentioned just be for tuning the tRD?

Anyway, I'm not reading the threads I need to read to be able to give a valuable input on this one, Before. I promise that when I've finished with my current review I will have a closer look on what you posted on IxtremTek and other related articles and will try to have a good view on tRD and related timings

Thanks for the table

[before]

You know, I don't have access to confidential Intel datasheets, so I'm just like you; trying to understand out of a purely chaotic environnement. This table consists of only 10 lines taken out of 256.

MCHBAR registers commented into public datasheets aren't the ones you wanna play with / or the way they are commented is too poor to give you a sufficient amount of knowledge. At least, that's how I feel it.

The matter here is, what we actually called tRD? Is it more a MCH or a DRAM process? Is it a single timing or a timings gathering?

This article at Amandtech is interesting, no doubt about that. BTW, no one can just conclude that because we have found an offset which increase memory bandwidth; this offset is tRD. Also, here, I mean concerning PLVL, we don't talk about a single offset, but 2 different offsets, each one located among registers for DRAM timings, respectively for CH0 and CH1. At a first glance, both PLVL don't look like to be more MCH related than DRAM related...

There are several other offsets which have an effect on bandwidth or latency. I've talked about 03Fh earlier in this thread, but there are others as well. And those I'm thinking about consist only in an unique offset; purely MCH related.

[KTE]

On the Intel boards I played with (P35) PL was directly related to what tRFC you set in BIOS, the DRAM ratio and the FSB. This below image is at +0.0 MCH voltage above stock and I could bench it:



The compromises were three:
-Use 2:3 RAM divider with decent vMCH and vDDR.
-Boot at a low FSB (266 strap) with a moderate tRFC (35 for 30 1066 rated) and use SetFSB.
-Set high tRFC at boot and then you'll need high vDIMM to drop tRFC in Windows. The above ss was at 2.18V real and 2.2V BIOS and the max it could drop tRFC was 38 at those volts (52 boot). With 2.3V BIOS, I've benched 626 5-5-5-5 75ns tRFC and at PL6/7 it will do 600 5-5-5-5 at tRFC 20 with the same volts.

Its done PL4 600 a few days ago with stock vMCH, stock vDDR but by booting 266FSB>SetFSB and high boot tRFC.




I don't know if PL4 is even theoretically possible though on P35, meaning if such a hardware register does exist.

What before said is correct though. Your timings are hardware (HEX) encoded to certain total timing setups (complete settings), so some combinations are possible while others aren't even if they show up (i.e. tRTC/tRP/tRAS at 2/1 is not possible by P35/X38 though many times you can select such an option [empty register= no actual change]. But the system at boot has to run a set of quick calculations of aggregate timings (many) and that's how it sets/allows some timings and not others. Those values are MCH/DRAM fixed and with AMD systems, they're DRAM and IMC fixed.

Such as why you can't have less than tRC 11 with Phenom: no register encoding within IMC for it.

[massman]

PL=4 is very low, quite a result, KTE . Did you boot at PL4?

Regarding the article on Anand, I don't think you should doubt it so much, Before . Kris (FreeCableGuy) has quite some knowledge and he's not just guessing.

I'm leaning towards saying that the perfomance level (tRD) is MCH process as the terms "tRD", "read delay" or "performance level" are not found in the Jedec DDR2 datasheet.

[KTE]

Yep massman, bootup. No way can I change PL below 6 in Windows, ever. Max I can drop it to is 6 myself unless I get it to boot lower. It looks to be a function of the total timings and latencies to me as well as the vMCH.

MCH as well as RAM obviously would both effect timings, clocks and performance, that's a given. The name itself describes its function well enough. That's exactly why K10h/Nehalem will have the memory controller within the CPU and you can tell the difference of how that can effect RAM perf. if you compare K8 to K10 on memory (quite a few differences pretty clear with the same RAM/MB).

DRAM Controller within Memory Controller (in K10) allows Ganged and Unganged mode. One is quicker for RAM than the other overall, one is quicker in single threaded apps and the other in multi-threaded. One allows higher clocks and lower latencies than the other <- so memory controller will always effect the RAM perf/clocks/latencies very much as it's part of the total equation (just like FSB is).

EDIT: just read that article on X48... the tRD value looks like MaxAsyncLatency aka MaxReadLatency to me on AMD platforms. It is by far the hardest to drop but has massive bandwidth/latency/performance effect. I'm talking 100-500MB/s read gain in EVEREST just by one value dropping in Memset (is usually around 50 at >800).

[Pain|Killer]

Transaction booster has 2 levels in P5k deluxe. I tried to enable both 0 and 1 and also raised Vmch a little but it refuses to post.

So no way i can lower my PL no.?:confused

[KTE]

So no way i can lower my PL no.?:confused

Give your MCH +0.1V from stock and boot at 300x8 1:2. Then use SetFSB/Clockgen. You should get a low PL. Try it.

[M.Beier]

PL4... That sounds like a challenge... : - )

due low vdimm here's my shot for the day


I'll try PL4 tomorrow if I get some spare time...

[kiwi]

On Asus mbs it's called Transaction booster (or Performance level - new X48 mb) and you can either increase or decrease boost level depending on the value that is set depending on cpu FSB/CL

[Pain|Killer]

Give your MCH +0.1V from stock and boot at 300x8 1:2. Then use SetFSB/Clockgen. You should get a low PL. Try it.

At 333x9 I get PL 5. But I want PL 5 or 6 with FSB 400. Is it possible?

On Asus mbs it's called Transaction booster (or Performance level - new X48 mb) and you can either increase or decrease boost level depending on the value that is set depending on cpu FSB/CL

I am currently running Transaction booster at auto. If i enable it to whether 0 or level 1, it doesn't even post.

BTW Dram static read control is also very important. I first disable it and got PL11 but after enabling it, PL changed from 11 to 7. What is this?

[KTE]

Can't say much sorry, I usually stay clear of ASUS boards for everyday use due to past experience. I get PL4 at those settings but when choosing Extreme subtimings. Obviously your RAM/MCH has to be able to hack it in the first place.

[Blackbird_CaD_]

I have 4GB (4 sticks) of Corsair 6400C4 800 mhz ddr2.
I'm running them at 4-4-4-12 and 800 mhz, and i have a FSB of 400x9, my memory multiplier is 1:1
I have Dram static read control enabled.
And in MemSet it says my performance level is 15?? That's the highest possible.
What is wrong? There must be something wrong somehwere..