ASUS Maximus Formula SE

[NBK]

yup some for helping me on the forum, some for PM some heck for posting..

thats how i solved the issue..
no harm right..

hmm is the e8500 out yet in the us?? on retail??

Hi

The retail E8500 was out in the US and then it vanished. I have heard that it was supposed to reappear on 11 Feb 2008 or in April 2008. The truth is no one knows...

HTH
NBK

[Aurhinius]

My findings

FSB 400 266 STRAP Mem 1000mhz 4,4,4,12 TRD 6 (Board just won't do TRD 5) divider 5:4 - Everest bandwidth 8800 latency 53ns

FSB 450 400 STRAP Mem 1200mhz 5,5,5,12 TRD 7 divider 4:3 - Everest Bandwidth 9996 latency 51ns

So far it seems the extra mhz on the FSB is still the winner and I think there is something going on with the X38 that is different from the X48.

Always thought lower strap was better... guess not or the board has been optimised better for higher straps.

can you shed any light on this Tony?

Okay did a bit more testing and managed to get a TRD of 5 in certain circumstances by dropping AI clock twister to moderate instead of strong.

Tested FSB 400, 266 STAP, 5,5,5,12 , 3:2 divider 1200mhz TRD 5 everest 9500 52ns
will not boot 400, 266, 5:4, 4,4,4,12 TRD 5

[Aurhinius]

My findings

FSB 400 266 STRAP Mem 1000mhz 4,4,4,12 TRD 6 (Board just won't do TRD 5) divider 5:4 - Everest bandwidth 8800 latency 53ns

FSB 450 400 STRAP Mem 1200mhz 5,5,5,12 TRD 7 divider 4:3 - Everest Bandwidth 9996 latency 51ns

So far it seems the extra mhz on the FSB is still the winner and I think there is something going on with the X38 that is different from the X48.

Always thought lower strap was better... guess not or the board has been optimised better for higher straps.

can you shed any light on this Tony?

Okay did a bit more testing and managed to get a TRD of 5 in certain circumstances by dropping AI clock twister to moderate instead of strong.

Tested FSB 400, 266 STAP, 5,5,5,12 , 3:2 divider 1200mhz TRD 5 everest 9500 52ns
will not boot 400, 266, 5:4, 4,4,4,12 TRD 5

So seems my board just can't do TRD of less than 7 at 450 FSB also seems like any memory latency below 50 ns is a no go....

Thoughts?