Intel's First Nehalem Cpu-Z Pic.

[Lestat]

goodness gracious if the damn thing reports everything incorrectly why the heck do we use it

abolish it!

it's no different than any other app. it needs to be updated to support new hardware and features of said hardware.
anytime you use an old CPU-Z on a newer CPU it reads things funky.

as for someone's comment on the quality. look at everyone elses screenies, they are the same.
its called jpeg compression

[gallardo]

Errm... isn't Windows XP limited to 4 threads? Or was it 8? Cause I'm pretty sure it doesn't support 16 friggin threads!

[Movieman]

goodness gracious if the damn thing reports everything incorrectly why the heck do we use it

abolish it!

Oh I hope Franck isn't reading this or you'd have one pissed Frenchman on your backside.
Abolish one of the best little utilities that exists just because it misreads a cpu that won't be released for another 6-9months?
Think about that a minute

The internet collapses into a black hole.

Very good,I liked this one!

[mike8913]

8 SMP clients......shwing!!!

[NapalmV5]

wow dudes stop it! i didnt mean to turn the thread into anti-cpuz lol

Enjoy, i simply asked! but i got really annoyed by your them annoying smilies

[EnJoY]

Enjoy, i simply asked! but i got really annoyed by your them annoying smilies

Don't get mad at me, I didn't make em.

[Craftyman.]

wow dudes stop it! i didnt mean to turn the thread into anti-cpuz lol

Enjoy, i simply asked! but i got really annoyed by your them annoying smilies

RESISTANCE IS FUTILE

[Swatrecon_]

my vote goes to fake.

[[LCN]Knowledge]

Hi, I agree with Lestat. When you export a file to JPEG it will be exported with the default compression (60% in Photoshop, MSPaint etc.) which isn't very good but it is intended for a considerable small file size. If you rise the quality to say 100% the file size will increase in 200-300%.

For the L2 cache, I guess 256KBx4 wouldn't be that bad, because it will have L3 cache too, maybe the new Intel Arch. wont need too big L2 cache. I don't know much about L3 cache but I think it would be sad to have 8MB of it just sitting there doing nothing?

[Lestat]

Errm... isn't Windows XP limited to 4 threads? Or was it 8? Cause I'm pretty sure it doesn't support 16 friggin threads!

XP-Pro is only good for 2 physical cpu's with up to 32 total threads.
so these cpu's. quad cores w/ hyperthreading = 16 threads.

[Zytek_Fan]

it's no different than any other app. it needs to be updated to support new hardware and features of said hardware.
anytime you use an old CPU-Z on a newer CPU it reads things funky.

as for someone's comment on the quality. look at everyone elses screenies, they are the same.
its called jpeg compression

Yeah it doesn't have the usual markings of a fake. And it could very well be real. Remember that Nehalem was shown WORKING at IDF San Francisco

[CoolZone]

after we see some benches,we can decide if it is true or fake

[Zytek_Fan]

after we see some benches,we can decide if it is true or fake

That won't happen.

[sierra_bound]

Because of a likely non-disclosure agreement, you probably won't see much more than that CPU-Z shot. And given the fact that Intel demonstrated a working Nehalem system (complete with task manager screenshot) back in September at its developer's forum, there's no reason to doubt that someone else would have a similar system at this point, especially in Asia.

[JAG87]

Because of a likely non-disclosure agreement, you probably won't see much more than that CPU-Z shot. And given the fact that Intel demonstrated a working Nehalem system (complete with task manager screenshot) back in September at its developer's forum, there's no reason to doubt that someone else would have a similar system at this point, especially in Asia.

can we have his address? does he have life insurance?

[sierra_bound]

The screenshot was posted today on an Asian website. Google is your friend.

http://www.chiphell.com/?action-viewnews-itemid-178

[Zytek_Fan]

...and ChipHell is usually among the first to leak info

[sokarul]

What happens when we are done with the nanometers?

Photonics

[Jowy Atreides]

What happens when we are done with the nanometers?

picometers?

LOL

[Movieman]

wow dudes stop it! i didnt mean to turn the thread into anti-cpuz lol

Enjoy, i simply asked! but i got really annoyed by your them annoying smilies

I don't know what your talking about!

[Movieman]

The numbers given by CPU-Z kinda makes sense to me from the insignificant sources I have.

To me, it wouldn't make sense to test both QP and a new architecture together at present time, as they are both independent technologies. Could be me, but testing QP with a proved CPU + testing Nehalem with a proved FSB / connection is sensible. When both are satisfactory in terms of expectations, then the tests of combining them could begin. Just don't makes sense to test multiple new technologies all at the same time, as problem / error finding complexity increases.

Just speculating, of course, as I really don't have any insights into how the protocol is for testing these kinda of things.

Whether your right or wrong what you say makes good common sense and may well be true.

[savantu]

...
Nehalem comes in two flavors: one uses the old FSB, and one uses QuickPath (CSI). This one seems to be the one using the old FSB.

No, it doesn't.

There's a QPI version and one without.

The one without dispenses completely with the NB , it is fully integrated in the CPU ( IMC+PCI-E+DMI connector).The CPU links directly to the SB with the DMI link which is based on PCI-E.

It is strange , because it's completely different .You don't have frequency as multiplier x interface link , simply because there isn't any interface like we were used to ( FSB , HT ).

[savantu]

Nehalem has an IMC version, and one thats still going to use a NB as far as I have read.

Well , both have IMC , one will use NB ( QPI enabled ) and one won't.See my previous post.

I'd like to comment a little on the low L2.If the picture is true , then Holy Jesus!That's utterly different from what I expected. ( 64KB L1s and 8MB shared L2 )

I'd wager that the small 256KB L2 isn't a typical L2 as we know it. ( Instruction+Data ).I'd say if the photo is true , the L2 is an L2I or instruction cache ( holds only instructions , not data - that approach was done on Montecito Itanium , the L2 there is split into 1MB L2I and 256KB L2D ).
The L3 should be extremely fast , like on Itanium ( 14-20 cycles , that's L2 territory ) and data should go directly to the L1.The L1s need to be extremely fast too.

What are the implications if all the above are true : low frequency scalability.As for performance, it's strange.I doubt this cache structure is superior to that of Core , in fact I'd say it is inferior.

[NapalmV5]

Don't get mad at me, I didn't make em.

RESISTANCE IS FUTILE

I don't know what your talking about!

u guys are.. u guys are..

[xlink]

if its indeed real.. why such a low fsb?

might use the system bus of Itanium...

gosh if quick path is being used itanium side...
why is it such a stretch to figure this going itanium side.

FYI the itanium bus is a lot broader.