Official DFI LanParty UT X38-T2R(and LT) Discussion/Review/Overclock/Guide Thread

[lazy]

im putting nearly 1.5v to the nb and 2.27 to the ram and it wont boot stock settings for tracers.. do i need to rma these ?

[eva2000]

Hasn't made any difference for me but would be worth a shot.


They're from a company called AG Devices. They have different interchangeable heads also. This one's handy for dual measurements on an SMD device.

cool.. how much did it cost ya ?

im putting nearly 1.5v to the nb and 2.27 to the ram and it wont boot stock settings for tracers.. do i need to rma these ?

pay attention to which mem dividers you use prior to 12/28 bios 5:8 divider won't boot your system

12/28 Beta Bios - 5:8 divider tests
Previously on 11/28 bios, certain memory dividers had stability issues. 4:5 divider couldn't do more than 440FSB, 3:5 divider had issues of stability even at 333FSB due to tight performance level of 4 and 5:8 divider wouldn't even allow system to boot regardless of cpu FSB set.

Now 12/28 beta bios http://www.dfi.com.tw/Support/Downlo...FLAG=B&SITE=US has at least moved one step closer, with fixing the 5:8 divider.

From 11/28 bios 5:8 no system boot, to 12/28 beta bios doing 400FSB 5:8 640Mhz 5-5-5-15 on memory! Having some difficulties tuning clock fine delay for above 400FSB on 5:8 so far since using 2x1GB Crucial Ballistix PC2-8500 Tracers on 2:3 divider manages upto 681mhz 5-5-5-x more easily!

5:8 divider needs slightly more vdimm than 2:3 divider but still pretty good for 640mhz 5-5-5-15 at 2.35v bios set.

Results

• Single Super Pi 32M = 13m 21.485ms
• Everest 4.20.1245 Beta Bandwidth

12/28 Beta Bios settings

PC Health Status
Adjust CPU Temp: +7

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 9x
- Target CPU Clock: 3600
CPU Clock: 400
Boot Up Clock: AUTO
DRAM Speed: 333/1066
- Target DRAM Speed: 1280
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.2875v
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.35v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.566
CPU VTT Voltage: 1.393
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: FAST 
- Enhance Addressing: FAST
- T2 Dispatch: Enabled 

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: More Aggressive
- DIMM 1 Clock fine delay: 1680 
- DIMM 2 Clock fine delay: 490
- DIMM 1 Control fine delay: 560
- DIMM 2 Control fine delay: 350
- Ch 1 Command fine delay: 350

Ch2 Clock Crossing Setting: More Aggressive
- DIMM 3 Clock fine delay: 1610
- DIMM 4 Clock fine delay: 490
- DIMM 3 Control fine delay: 560
- DIMM 4 Control fine delay: 350
- Ch 2 Command fine delay: 280

Ch1Ch2 CommonClock Setting: More Aggressive

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)

CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 5
Precharge Delay (tRAS): 15
All Precharge to Act: 4
REF to ACT Delay (tRFC): 35
Performance LVL (Read Delay) (tRD): 7

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: Auto 
- Channel 1 Phase 1 Pull-In: Auto
- Channel 1 Phase 2 Pull-In: Auto
- Channel 1 Phase 3 Pull-In: Auto
- Channel 1 Phase 4 Pull-In: Auto

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): 11
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): 3
ALL PRE to Refresh: 4

[Jor3lBR]

cool.. how much did it cost ya ?



pay attention to which mem dividers you use prior to 12/28 bios 5:8 divider won't boot your system

12/28 Beta Bios - 5:8 divider tests
Previously on 11/28 bios, certain memory dividers had stability issues. 4:5 divider couldn't do more than 440FSB, 3:5 divider had issues of stability even at 333FSB due to tight performance level of 4 and 5:8 divider wouldn't even allow system to boot regardless of cpu FSB set.

Now 12/28 beta bios [/code]

EVA,

For future references could you please inform the DDR BANKS your using (1,3 or 2,4)?

Thanks

[Praz]

cool.. how much did it cost ya ?

They're not cheap but once in while one will be on eBay for next to nothing.

QP02000 - Quick Probe Standard Probe, stand and Pogo Head assy - $65.00
QPDP300 - Viper, Dual Pin Probe Head assy. Only QP02000 also reqd. - $148.00

http://www.agdevices.com/downloadfil...price_list.pdf