Nehalem Info from hkepc

[Zytek_Fan]

It says 45nm, but we all now that Penryn is 45nm and Nahelem will be 32nm. If they got that wrong, no telling what else is inaccurate here.

I'm still trying to decide between a q9450 or waiting for Nahelem. I think the wise thing is to wait, as I doubt I will really need a quad before then.

Nehalem will initially be 45nm, but then there will be a refresh to turn it over to 32nm.

[adamsleath]

triple channel ddr3 mmmm 3gigs or 6 ?
will 3 sticks present oc problems?

32nm isnt until 2010....so intel have stated in their own preezuntayshuns

saving up for nehalem right now.

may get a yorky with some spare change...maybe

[Hornet331]

While it's nice and all with new awesome expectations/promises among new products which this news is FULL of it also sucks a bit for my wallet as I have intended to hold onto Penryn for a while as Nehalem will prolly require a full upgrade for me, and this architecture sounds like it could have a serious lead over Core 2 Duo so it could be difficult holding onto C2D a long time.

Nehalem = Intel strenghtening the remaining weak points in Core 2 Duo.

good thing i switched to ddr3 now, i think my 2gb ddr3-1800 stick will also find some use in nehalem. But i dont think i buy into nehelem, maybe i'll wait for sandybridge.

[Pinnacle]

WOW that is just killer

[Epsilon84]

Please explain Core 2's biggest weakness again?

For a good example, have a look at the multi-CPU scaling in Cinebench 10, C2Q averages around ~3.6x IIRC, Phenom is around ~3.95x, almost linear scaling.

Now, I'm aware that end performance is still in Intel's favour, but the fact remains that per core scaling is less than ideal, and can be improved. Nehalem should address that.

C2Q is a strong CPU but it is not perfect.

[AliG]

when does the native octo core come out? Is that with the 45nm refresh or the initial launch? As 16 threads could be very useful, I may even consider folding with one of those

[Blauhung]

when does the native octo core come out? Is that with the 45nm refresh or the initial launch? As 16 threads could be very useful, I may even consider folding with one of those

i think it's being called Nehalem EX externaly right now, and that will be a 4 socket server only product. Due to the die size, pretty much everyone here wouldn't want to pay the margins that will be placed on it by the manufacturing costs associated with it. But i believe it's slatted to come out along side the 32nm refresh of nehalem (westmere if i am remembering right). until then Dunnington with 6 penryn like cores will fill the 4 socket market segment when it makes it out something later this year.

[Donnie27]

For a good example, have a look at the multi-CPU scaling in Cinebench 10, C2Q averages around ~3.6x IIRC, Phenom is around ~3.95x, almost linear scaling.

Now, I'm aware that end performance is still in Intel's favour, but the fact remains that per core scaling is less than ideal, and can be improved. Nehalem should address that.

C2Q is a strong CPU but it is not perfect.

Thanks E, I get it!

I'm not thinking FSB is a great. I just don't think it is that BIG weakness that's all. I'm not saying its layout is great or nothing is wrong with it or even that it couldn't be better. IMHO, I'm NOT seeing the this terrible weakness being complained about. AMD has FAR worse problems than Intel's FSB that desperately needs to be address while folks are complaining about a FSB? Or Dual Socket systems with Two FSBs? Scratches head.

Why do I say this? If FSBs is this terrible, big weakness, then Nehalem should be more than 10 to 25% faster than the results leaked so far. If the FSB is sooo bad, just adding the EV6 like CSI to the Penryn should come close to those Nahalem results, right? I'm talking about 4 cores via MCM. Look at the difference IMC did for 7.5 to K8? K10 flopped because each of the four cores wasn't improved enough. Doesn't matter what kind of a bus it rides or if its native or not. Intel has gotten a lot out of that FSB!

Find something a little more Optimized, so the 4 cores can be stressed. The FSB doesn't choke 4 cores and scale well with most apps. They scale well with software that allows them too, that's an X86 problem, not a FSB problem.

http://www.lostcircuits.com/cpu/intel_yorkfield/

And see which ones I'm talking about.

[fireice2]

Nice thing is that current coolers may not have compatibility issues with the new socket.

[Donnie27]

Oh yes Core 2 Duo is perfection. I just think you forget how much code is serial.

And you forgot how much is still Paralelle and Random! Yeah you are right some many times that I learned a long time ago no to argue with ya'.

Just as I said Intel would use 3 (cheap), 6 and 9 slots.

[StealthyFish]

They said a new socket would be introduced for Nehalem with the IMC and the new transport bus

those sockets are fun. They're huge compared to LGA775 (seen em =D), and CSI has arrived =D

Thanks E, I get it!

I'm not thinking FSB is a great. I just don't think it is that BIG weakness that's all. I'm not saying its layout is great or nothing is wrong with it or even that it couldn't be better. IMHO, I'm NOT seeing the this terrible weakness being complained about. AMD has FAR worse problems than Intel's FSB that desperately needs to be address while folks are complaining about a FSB? Or Dual Socket systems with Two FSBs? Scratches head.

Why do I say this? If FSBs is this terrible, big weakness, then Nehalem should be more than 10 to 25% faster than the results leaked so far. If the FSB is sooo bad, just adding the EV6 like CSI to the Penryn should come close to those Nahalem results, right? I'm talking about 4 cores via MCM. Look at the difference IMC did for 7.5 to K8? K10 flopped because each of the four cores wasn't improved enough. Doesn't matter what kind of a bus it rides or if its native or not. Intel has gotten a lot out of that FSB!

Find something a little more Optimized, so the 4 cores can be stressed. The FSB doesn't choke 4 cores and scale well with most apps. They scale well with software that allows them too, that's an X86 problem, not a FSB problem.

http://www.lostcircuits.com/cpu/intel_yorkfield/

And see which ones I'm talking about.

FSB is a bottleneck for multiple core chips. If multiple cores all share the same small bus, there's the bottleneck, not just using multiple chips.

And from what I've seen, I wouldn't expect amazing Nehelem leaked specs out since they're still pretty new.... or so I've heard >.> . You can't expect the first few bins to be comparable to retail. But CSI isn't going to be very noticable in the consumer market. Not many consumers use the full bus, but in the server department, the FSB bottleneck is a glaring problem Intel has acknowledged before. Though FSB is highly optimized, there's more potential in the chips than what's already showing.

[OBR]

Hmm? There is no Bloomfield picture. But it contains 3 DDR3 channels on the IMC.

Look at original review, are you blind? I have seen Bloomfield + Tylersburg ...

[OBR]

why do they call flash memory nvram?

and tri channel mem is confusing...
the board has 4 slots... so... hows it supposed to work?

I see 6 slots ... look at original full review not only for some screens here ...

[JumpingJack]

It says 45nm, but we all now that Penryn is 45nm and Nahelem will be 32nm. If they got that wrong, no telling what else is inaccurate here.

I'm still trying to decide between a q9450 or waiting for Nahelem. I think the wise thing is to wait, as I doubt I will really need a quad before then.

Nope... Nehalem is the tock of the 'tick-tock' model. It will be 45 nm. Intel's manufacturing strategy is to offset architectural revisions 1 year from process revisions, and introduce new architectures every 2 years instead of every 4-6 years.

http://download.intel.com/technology...ence-paper.pdf

It started with cedarmill/presler/yonah at 65 nm, basically shrinks with minor archiectural tweaks on 65 nm from 90 nm (the tick), about half-way through merom/conroe/woodcrest were introduced on 65 nm (the 65 nm tock), next comes penryn/wolfdale/harpertown at 45 nm which is a shrink of merom/conroe/woodcrest with some minor architectural tweaks (the tick), and about 1/2 through (toward end of 2008) Intel will introduce the tock, a new architecure (Nehalem).

In the PDF I show, the next tick would be a 32 nm Nehalem-c, this has since recieved a new code name I believe called westmere, westmere will be a similar shrink and minor revision to Nehalem, and then Gesher will appear 1/2 through 32 nm for the tock.

It is a very rapid cadence, in one year Intel will introduce a new arch. to boost performance via IPC, the next year they will introduce a new process tech to help boost clocks or lower power.

I have my doubts that they will be able to keep up this rapid pace.... it is very agressive.

Jack

[naokaji]

And the change is? For me its still 30% less power. even tho 5 or 10% may come from a chipset.

I really dont care about where its saved. Just that it is saved.

yep.. and power consumption of nehalem looks especially good because they are integrating more stuff in the cpu (IMC).. so its really good that they can keep power usage "low".

[Shintai]

Look at original review, are you blind? I have seen Bloomfield + Tylersburg ...

Uhm..no..Maybe you should follow the context of the thread. I was answering Saaya about it. There is a picture in the review, but not in the start of the thread.

[Shintai]

yep.. and power consumption of nehalem looks especially good because they are integrating more stuff in the cpu (IMC).. so its really good that they can keep power usage "low".

Moving things around dont change power consumption.

[Shintai]

And you forgot how much is still Paralelle and Random! Yeah you are right some many times that I learned a long time ago no to argue with ya'.

Just as I said Intel would use 3 (cheap), 6 and 9 slots.

Please...you are on deep water it seems.

Random code? lol...thats a new. Also parallel code aka multithreaded is usually guided by a serialcoded thread that can only run on 1 CPU. So the others will have to share some data with that thread.

Also I dont know if you actually know. But its kinda normal for also shifting threads around udner workload between cores. Yet again an effect of why the FSB is a weakness.

Do you think its for fun that they write up to 2x performance boost with Nehalem over Penryn for multithreaded on a single chip? But only up to 1.25x with singlethread code? Thats one major leap in difference....

[naokaji]

Moving things around dont change power consumption.

thats a big fat for me...

i was just thinking integrating more stuff in the cpu without a increase in power usage = good. but your right, i somehow forgot that its stuff that would just be elsewhere...

[Helmore]

Do you think its for fun that they write up to 2x performance boost with Nehalem over Penryn for multithreaded on a single chip? But only up to 1.25x with singlethread code? Thats one major leap in difference....

That's partially due to SMT (aka HyperThreading) (and of course the fact that it's a single die solution.)

[hixie]

Am i the only one that noticed "Direct NAND"?

[savantu]

Moving things around dont change power consumption.

It does.

A typical Intel NB has 3 things : PCI-E controller , MC and DMI.
Nehalem gets all on die.The difference?

Until Nehalem NBs were typically 1 or 2 process generations behind. ( CPUs on 90nm NB were 130/180nm , CPUs 65nm NBs were 90nm/130nm ).

A NB typically burns 8-25w.Moving it inside the CPU and using the latest process tech will probably cut the power by 2-4x.

[savantu]

...
Do you think its for fun that they write up to 2x performance boost with Nehalem over Penryn for multithreaded on a single chip? But only up to 1.25x with singlethread code? Thats one major leap in difference....

When Intel states performance boost they typically refer to SPEC_INT/FP for single threaded performance and SPEC_INT/FP_rate for multithreaded.

Nehalem getting a 25% boost on single threaded code over Penryn is formidable.Why ?

Because compilers are tunned so well for Spec that Penryn's major weakness isn't affecting the single threaded stuff , in other words , they manage to keep the execution units full.Since Penryn is so wide and capable of issuing 4 DP FLOPs per cycle , I'm surprised Nehalem is able to increase the perf by such a margin.
It would make a Nehalem be almost 2x as fast for Spec_FP vs. a 3GHz K8.If that ain't an improvement , I don't know what it is.

[Shintai]

It does.

A typical Intel NB has 3 things : PCI-E controller , MC and DMI.
Nehalem gets all on die.The difference?

Until Nehalem NBs were typically 1 or 2 process generations behind. ( CPUs on 90nm NB were 130/180nm , CPUs 65nm NBs were 90nm/130nm ).

A NB typically burns 8-25w.Moving it inside the CPU and using the latest process tech will probably cut the power by 2-4x.

You can already get 65nm chipsets today to use with your 65nm CPU. So thats basicly just pragmatics. Also I dont hope a NB uses 25W...
If you note most of the powersavings is from a faster core. 30% less power consumption for the same performance as a Penryn. And if you have a scenario with 10-100% boost (Lowest single to highest multi). Then you have your 30% there.

[_Lone_Wolf_]

Nehalem getting a 25% boost on single threaded code over Penryn is formidable.Why ?

Assuming the PR material is refering to absolute performance rather than a per clock figure, and Nehalem is being touted as unlocking 45nm High K/metal gate potential wouldn't most of the increase be from a clock boost, possible even drawn from the turbo mode?

Moving things around dont change power consumption.

Dont off chip drivers consume very large amounts of power relative to on die buses? Elimination of a FSB link to the memory controller should reduce overall power consumption shouldn't it?